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AD6684

Data Sheet

Rev. 0 | Page 32 of 107

DIGITAL DOWNCONVERTER (DDC)

The AD6684 includes four DDCs that provide filtering and reduce

the output data rate. This digital processing section includes an

NCO, a half-band decimating filter, a finite impulse response

(FIR) filter, a gain stage, and a complex to real conversion stage.

Each of these processing blocks has control lines that allow it to be

independently enabled and disabled to provide the desired

processing function. Each pair of ADC channels has two DDCs

(DDC0 and DDC1) for a total of four DDCs. The digital down-

converter can be configured to output either real data or

complex output data.

The DDCs output a 16-bit stream. To enable this operation, the

converter number of bits, N, is set to a default value of 16, even

though the analog core only outputs 14 bits. In full bandwidth

operation, the ADC outputs are 9-bit words followed by seven

zeros, unless the tail bits are enabled.

DDC I/Q INPUT SELECTION

The AD6684 has four ADC channels and four DDC channels.

Each DDC channel has two input ports that can be paired to

support both real and complex inputs through the I/Q crossbar

mux. For real signals, both DDC input ports must select the

same ADC channel (that is, DDC Input Port I = ADC Channel A

and DDC Input Port Q = ADC Channel A). For complex

signals, each DDC input port must select different ADC

channels (that is, DDC Input Port I = ADC Channel A and

DDC Input Port Q = ADC Channel B, or DDC Input Port I =

ADC Channel C and DDC Input Port Q = ADC Channel D).

The inputs to each DDC are controlled by the DDC input selec-

tion registers (Register 0x0311 and Register 0x0331) in conjunction

with the pair index register (Register 0x0009). See Table 45 and

Table 46 for information on how to configure the DDCs.

DDC I/Q OUTPUT SELECTION

Each DDC channel has two output ports that can be paired to

support both real and complex outputs. For real output signals,

only the DDC Output Port I is used (the DDC Output Port Q is

invalid). For complex I/Q output signals, both DDC Output

Port I and DDC Output Port Q are used.

The I/Q outputs to each DDC channel are controlled by the

DDC complex to real enable bit, Bit 3 in the DDC control

registers (Register 0x0310 and Register 0x0330) in conjunction

with the pair index register (Register 0x0009).

The Chip Q ignore bit in the chip mode register (Register 0x0200,

Bit 5) controls the chip output muxing of all the DDC channels.

When all DDC channels use real outputs, set this bit high to

ignore all DDC Q output ports. When any of the DDC channels

are set to use complex I/Q outputs, the user must clear this bit

to use both DDC Output Port I and DDC Output Port Q. For

more information, see Figure 81.

DDC GENERAL DESCRIPTION

The four DDC blocks are used to extract a portion of the full

digital spectrum captured by the ADC(s). The DDC blocks are

intended for IF sampling or oversampled baseband radios

requiring wide bandwidth input signals.

Each DDC block contains the following signal processing stages:



Frequency translation stage (optional)



Filtering stage



Gain stage (optional)



Complex to real conversion stage (optional)

Frequency Translation Stage (Optional)

This stage consists of a 48-bit complex NCO and quadrature

mixers that can be used for frequency translation of both real

and complex input signals. This stage shifts a portion of the

available digital spectrum down to baseband.

Filtering Stage

After shifting down to baseband, this stage decimates the

frequency spectrum using a chain of up to four half-band, low-

pass filters for rate conversion. The decimation process lowers the

output data rate, which in turn reduces the output interface rate.

Gain Stage (Optional)

To compensate for losses associated with mixing a real input

signal down to baseband, this stage adds an additional 0 dB or

6 dB of gain.

Complex to Real Conversion Stage (Optional)

When real outputs are necessary, this stage converts the complex

outputs back to real by performing an fS/4 mixing operation

plus a filter to remove the complex component of the signal.

Figure 73 shows the detailed block diagram of the DDCs

implemented in the AD6684.

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