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AD6684 Datasheet(PDF) 83 Page - Analog Devices |
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AD6684 Datasheet(HTML) 83 Page - Analog Devices |
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83 / 107 page ![]() Data Sheet AD6684 Rev. 0 | Page 83 of 107 Address Name Bits Bit Name Settings Description Reset Access 0x0003 Pair map chip type [7:0] CHIP_TYPE Chip type. 0x3 R 0x3 High speed ADC. 0x0004 Pair map chip ID LSB [7:0] CHIP_ID Chip ID. 0xDC R 0x0006 Pair map chip grade [7:4] CHIP_SPEED_GRADE Chip speed grade. 0x0 R 0101 500 MHz. [3:0] Reserved Reserved. 0x0 R 0x0008 Pair map device index [7:2] Reserved Reserved. 0x0 R 1 Channel B/Channel D 0x1 R/W 0 ADC Core B/ADC Core D does not receive the next SPI command. 1 ADC Core B/ADC Core D receives the next SPI command. 0 Channel A/Channel C 0x1 R/W 0 ADC Core A/ADC Core C does not receive the next SPI command. 1 ADC Core A/ADC Core C receives the next SPI command. 0x0009 Global map pair index [7:2] Reserved Reserved. 0x0 R 1 Pair C/D 0x1 R/W 0 ADC Pair C/D does not receive the next read/ write command from the SPI interface. 1 ADC Pair C/D does not receive the next read/ write command from the SPI interface. 0 Pair A/B 0x1 R/W 0 ADC Pair A/B does not receive the next read/ write command from the SPI interface. 1 ADC Pair A/B receives the next read/write command from the SPI interface. 0x000A Pair map scratch pad [7:0] Scratch pad Chip scratch pad register. This register provides a consistent memory location for software debug. 0x07 R/W 0x000B Pair map SPI revision [7:0] SPI_REVISION SPI revision register (0x01 = Revision 1.0). 0x1 R 00000001 Revision 1.0. 0x000C Pair map vendor ID LSB [7:0] CHIP_VENDOR_ID[7:0] Vendor ID. 0x56 R 0x000D Pair map vendor ID MSB [7:0] CHIP_VENDOR_ID[15:8] Vendor ID. 0x4 R 0x003F Channel map chip power- down pin 7 PDWN/STBY disable This bit is used in conjunction with Register 0x0040. 0x0 R/W 0 Power-down pin (PDWN/STBY) enabled; global pin control selection enabled (default). 1 Power-down pin (PDWN/STBY) disabled/ ignored; global pin control selection ignored. [6:0] Reserved Reserved. 0x0 R |
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