PC87303 datasheet(25/114 Pages) NSC

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20 Configuration Registers (Continued)

Bits 3 4

Reserved

Bit 5

Selective Lock bit Unlike bit 6 of PTR which

locks all configuration bits this bit only enables

locking of the following

Bit 5 of PMC bit 4 of FER bits 0 – 7 of FAR bits

2 3 of PTR bit 1 of FCR and bit 5 of KRR Once

this bit has been set by software it can only be

cleared by a hardware reset It should be used

instead of bit 6 of PTR if a configration bit should

be dynamically modified by software (eg PMC

bits)

0 No lock except via bit 6 of PTR

1 Any write to the above configuration bits is ig-

nored (until a hardware reset which clears this

bit)

Bit 6

Parallel Port TRI-STATE Control bit

0 When this bit is 0 it does not affect the parallel

port pins

1 The parallel port outputs except the config-

ured IRQ line (IRQ5 or IRQ7) are in TRI-

STATE when either the parallel port is dis-

abled or the chip is in power-down mode

Bit 7

Reserved

258 Tape UARTs and Parallel Port Configuration Reg-

ister (TUP Index e 07h)

The TUP Register is cleared to XXXXX0XX on reset

Bit 1

Reserved

Bit 2

EPP Timeout Interrupt Enable bit

When this bit is 0 the EPP timeout interrupt is

masked

When this bit is 1 the EPP timeout interrupt is

generated on the selected IRQ line (IRQ5 or

IRQ7) according to bits 46 of PCR

Bits 3 – 7

Reserved

259 SuperIO Identification Register

(SID Index e 08h)

The SID Register is accessed like the other configuration

registers through the Index Register This read-only register

is used to identify the PC87303 chip

TLC12074 – 86

2510 Advanced SuperIO Configuration Register

(ASC Index 09h)

During reset bits 0 – 2 and bit 5 are initialzed to 0 and bits 6 –

7 are initialized to 1

Bit 0

IRQ5DRATE0 select

0 Pin 16 is IRQ5

1 Pin 16 is ADRATE0 open drain output

Selection of parallel port interrupt pin (IRQ5 or

IRQ7) via bits 1 and 0 of FAR and via bit 3 of

PTR is ignored and IRQ7 is used as parallel port

interrupt Unlike IRQ5 ADRATE0 is not con-

trolled by bits 6 and 5 of PCR it has the same

value as DRATE0

Bit 1

DRVE DR23 select

0 Pin 78 is DRV2

1 Pin 78 is DR23

DR23 is asserted when either drive 2 or drive 3 is

accessed

(except

during

logical

drive

ex-

changesee bit 3 of TDR)

The value of DR23 is undefined when working

with four drives encoding (bit 4 of FER is 1) The

PC87303 assumes DRV2 is 1 when bit 1 of ASC

is 1

Bit 2

Enhanced TDR support

0 TDR read is a function of bit 0 of FCR configu-

ration register

Pin 90 is IOCS16

Pin 87 is IDEHI VLD0

1 Pin 90 is DRID0 input

The PC87303 assumes IOCS16 is active when

bit 2 of ASC is 1

Pin 87 is DRID1VLD0 input

Bit 2 of ASC should be set to one before the FDD

is accessed thus preventing contention between

IDEHI and DRID1

The PC87303 provides full TDR support

Bit 3

Reserved bit On ASC writes this bit must be

written with a 0 On ASC reads the value is un-

defined

Bit 4

Reserved

Bit 5

The value of this pin is reflected on bit 3 of

CNFGA ECP register

Bits 6 7

System Operation Mode The PC87303 can be

configured to either PC-AT PS2 or Model 30

modes

00 Model 30 mode

01 PS2 mode

10 Reserved and illegal

11 PC-AT mode

2511 Chip Select 0 Configuration Register 0 (CS0CF0

Index e 0Ah)

This register holds the low address bits of the monitored IO

address See CS0CF1 register for complementary descrip-

tion Bit 0 holds A0

2512 Chip Select 0 Configuration Register 1 (CS0CF1

Index e 0Bh)

This register controls the behavior of the CS0 pin CS0 is

asserted on non-DMA PIO cycles when RD or WR is as-

serted CS0 can be asserted three ways 1) only on reads

2) only on writes or 3) on all PIO cycles The register is

initialized to 0 during reset

Bits 0 – 2

High address bits of the monitored IO address

Bit 2 holds A10 bit 1 holds A9 and bit 0 holds A8

Bit 3

Reserved

Bit 4

Enable CS0 assertion on write cycles

Bit 5

Enable CS0 assertion on read cycles

Bit 6

Enable full address-decoding

0 Decode only address bits A9 – A0 Ignore ad-

dress bit A10

1 Decode address bits A10 – A0

PC87303 Datasheet(PDF) 25 Page - National Semiconductor (TI)

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