PC87303 datasheet(26/114 Pages) NSC

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20 Configuration Registers (Continued)

Bit 7

CS0 Select Bit

0 Pin2isCS input

1 Pin 2 is CS0 output The PC87303 assumes

that CS input is 1 thus bit 6 of KRR must be 1

to access the KBC

2513 Chip Select 1 Configuration Register 0 (CS1CF0

Index e 0Ch)

This register holds the low address bits of the monitored IO

address See CS1CF1 register for complementary descrip-

tion Bit 0 holds A0

2514 Chip Select 1 Configuration Register 1 (CS1CF1

Index e 0Dh)

This register controls the behaviour of the CS1 pin CS1 is

asserted on non-DMA PIO cycles when RD or WR is as-

serted CS1 can be asserted in three ways 1) only on reads

2) only on writes or 3) on all PIO cycles The register is

initialized to 0 during reset

Bits 0 – 2

High address bits of the monitored IO address

Bit 2 holds A10 bit 1 holds A9 and bit 0 holds A8

Bit 3

Reserved

Bit 4

Enable CS1 assertion on write cycles

Bit 5

Enable CS1 assertion on read cycles

Bit 6

Enable full address-decoding

0 Decode only address bits A9 – A0 Ignore ad-

dress bit A10

1 Decode address bits A10 – A0

Bit 7

CS1 Select Bit

0 Pin 23 is SYSCLK

1 Pin 23 is CS1 output The PC87303 assumes

that SYSCLK input is 1 thus bit 7 of KRR must

be 0 to operate the KBC

26 POWER-DOWN OPTIONS

There are various methods for entering the power-down

mode All methods result in one of three possible modes

This section associates the methods of entering power-

down with the resulting mode

Mode 1

The internal clock stops for a specific function (ie

UART1 andor UART2 andor FDC)

This mode is entered by any of the following actions

1 Clear the FER bit for the specific function that is powered

down See Section 251 FER bits 1 – 3

2 During reset set certain CFG 0 – 4 pins See Table 2-1

3 Execute the FDC Mode Command with PTR bit 1 e 0

(XTALCLK) See Section 426 LOW PWR

4 Set Data Rate Select Register bit 6 in the FDC high with

PTR bit 1 e 0 See Section 36 bit 6

Mode 2

The internal clocks are stopped for all enabled

functions

Note

Clocks to disabled functions are always inactive

This mode is entered by any of the following actions

1 Clear all FER bits for any enabled function See Section

251 FER bits 1 – 3

2 Clear PTR bits 1 (XTALCLK) and 2 (CSOUTPWDN se-

lect) Then assert the PWDN signal low See Section

253 PTR bits 12 and Section 10 PWDN pin

3 Clear PTR bit 1 and then set PTR bit 0 (power-down)

high See Section 253 PTR bits 0 and 1

Mode 3

The external crystal is stopped and internal clocks

are stopped for all enabled functions

This mode is entered by any of the following actions

1 Clear all FER bits that enable the FDC UART1 and

UART2 functions See Section 251 FER bits 1 – 3

2 Set PTR bit 1 (XTALCLK) clear PTR bit 2 (CSOUT

PWDN select) Then assert the PWDN signal low See

Section 253 PTR bits 12 and Section 10 PWDN pin

3 Set PTR bit 1 and then set PTR bit 0 high See Section

253 PTR bits 0 and 1

4 During reset pull CFG0 – 4 pins high

5 Execute the FDC Mode Command with PTR bit 1 e 1

See Section 426 LOW PWR

6 Set Data Rate Select Register bit 6 in the FDC high with

PTR bit 1 e 1 See Section 36 bit 6

27 POWER-UP PROCEDURE AND CONSIDERATIONS

271 Crystal Stabilization

If the crystal is stopped by putting either the FDC or the

UARTs into low power mode then a finite amount of time

(E8 ms) must be allowed for crystal stabilization during

subsequent power-up

The stabilization period can be

sensed by reading the Main Status Register in the FDC if

the FDC is being powered up (The Request for Master bit is

not set for E8 ms) If either one of the UARTs are being

powered up but the FDC is not then the software must

determine the E8 ms crystal stabilization period Stabiliza-

tion of the crystal can also be sensed by putting the UART

into local loopback mode and sending bytes until they are

received correctly

272 UART Power-Up

The clock signal to the UARTs is controlled through the

Configuration Registers (FER PTR) In order to restore the

clock signal to one or both UARTs the following conditions

must exist

1 The appropriate enable bit (FER 12) for the UART(s)

must be set

2 and the power-down bit (PTR 0) must not be set

3 and if the PWDN pin option (PTR 2) is used the

CSOUT PDWN pin must be inactive

If the crystal has been stopped follow the guidelines in Sec-

tion 271 before sending data or signalling that the receiver

channel is ready

273 FDC Power-Up

The clock signal to the FDC is controlled through the Con-

figuration Registers the FDC Mode Command and the Data

Rate Select Register In order to restore the clock signal to

the FDC the following conditions must exist

1 The appropriate enable bit (FER 3) must be set

2 and the power-down bit (PTR 0) must not be set

3 and if the PWDN pin option (PTR 2) is used the

CSOUT PDWN pin must be inactive

In addition to these conditions one of the following must be

done to initiate the recovery from power-down mode

1 Read the Main Status Register until the RQM bit (MSR7)

is set or

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