PC87303 datasheet(65/114 Pages) NSC

65 / 114 page

50 FDC Functional Description

(Continued)

After a hardware (assuming the FDC is enabled in the FER)

or software reset the Main Status Register is immediately

available for read access by the mP It will return a 00h value

until all the internal registers have been updated and the

data separator is stabilized When the controller is ready to

receive a command byte the MSR will return a value of 80h

(Request for Master bit is set) The MSR is guaranteed to

return the 80h value within 25 ms after a hardware or soft-

ware reset All other user addressable registers other than

the Main Status Register and Data Register (FIFO) can be

accessed at any time even while the part is in reset

60 Serial Ports

Each of these serial ports functions as a serial data input

output interface in a microcomputer system The system

software determines the functional configuration of the

UARTs via a 8-bit bidirectional data bus

The UARTs are completely independent They perform

serial-to-parallel conversion on data characters received

from a peripheral device or a MODEM and parallel-to-serial

conversion on data characters received from the CPU The

CPU can read the complete status of either UART at any

time during the functional operation Status information re-

ported includes the type and condition of the transfer opera-

tions being performed by the UART as well as any error

conditions (parity overrun framing or break interrupt)

The UARTs have programmable baud rate generators that

are capable of dividing the internal reference clock by divi-

sors of 1 to (216 – 1) and producing a 16x clock for driving

the transmitter logic Provisions are also included to use this

16x clock to drive the receiver logic The UARTs have com-

plete MODEM-control capability and a prioritized interrupt

system Interrupts can be programmed to the user’s require-

ments minimizing the computing required to handle the

communications link

61 SERIAL PORT REGISTERS

Two identical register sets one for each channel are in the

PC87303 All register descriptions in this section apply to

the register sets in both channels See Table 6-1

TABLE 6-1 PC87303 UART

DLAB1

Selected Register

Receiver Buffer (Read)

Transmitter Holding (Write)

Interrupt Enable

Interrupt Identification (Read)

FIFO Control (Write)

Line Control

MODEM Control

Line Status

MODEM Status

Scratch

Divisor Latch

(Least Significant Byte)

Divisor Latch

(Most Significant Byte)

62 LINE CONTROL REGISTER (LCR)

ReadWrite

The system programmer uses the Line Control Register

(LCR) to specify the format of the asynchronous data com-

munications exchange and set the Divisor Latch Access bit

This is a read and write register Table 6-2 shows the con-

tents of the LCR Details on each bit follow

TLC12074 – 27

FIGURE 6-1 PC87303 Composite Serial Data

Bits 01

These two bits specify the number of data bits in

each transmitted or received serial character The

encoding of bits 0 and 1 is as follows

Bit 1

Bit 0

Data Length

5 Bits

6 Bits

7 Bits

8 Bits

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