PC87303 datasheet(57/114 Pages) NSC

57 / 114 page

50 FDC Functional Description

The PC87303 is software compatible with the DP8473 and

82077 floppy disk controllers Upon a power on reset the

16-byte FIFO will be disabled Also the disk interface out-

puts will be configured as active push-pull outputs which

are compatible with both CMOS inputs and open-collector

resistor terminated disk drive inputs The FIFO can be en-

abled with the Configure command The FIFO can be very

useful at the higher data rates with systems that have a

large amount of DMA bus latency or with multi-tasking sys-

tems such as the EISA or MCA bus structures

The FDC will support all the DP8473 Mode command fea-

tures as well as some additional features Additional fea-

tures include control over the enabling of the FIFO for reads

and writes a Non-Burst mode for the FIFO a bit that will

configure the disk interface outputs as open-drain outputs

and programmability of the DENSEL output

51 MICROPROCESSOR INTERFACE

The FDC interface to the microprocessor consists of the

A9 – A3 AEN RD and WR lines which access the chip for

reads and writes the data lines D7 – 0 the address lines

A2 – 0 which select the appropriate register (see Table 3-1)

the IRQ6 signal and the DMA interface signals DRQ

DACK and TC It is through this microprocessor interface

that the floppy controller receives commands transfers

data and returns status information

52 MODES OF OPERATION

The FDC has three modes of operation PC-AT mode PS2

mode and Model 30 mode which are determined by the

state of the IDENT pin and MFM pin IDENT can be tied

directly to VDD or GND The MFM pin must be tied high or

low with a 10 kX resistor (there is an internal 40 kX –50 kX

resistor on the MFM pin) The state of these pins is interro-

gated by the controller during a chip reset to determine the

mode of operation See Section 30 Register Description for

more details on the register set used for each mode of oper-

ation After chip reset the state of IDENT can be changed

to change the polarity of DENSEL (see Section 10 Pin De-

scription)

PC-AT Mode

Bits 7 6 of ASC register are 11 (default)

The PC-AT register set is enabled The DMA enable bit in

the Digital Output Register becomes valid (IRQ6 and DRQ

can be TRI-STATE) TC and DENSEL become active high

signals (defaults to a 525

floppy drive)

PS2 Mode

Bits 7 6 of ASC register are 01 This mode

supports the PS2 Models 506080 configuration and reg-

ister set The DMA enable bit in the Digital Output Register

becomes a don’t care (IRQ6 and DRQ signals are always

valid) TC and DENSEL become active low signals (default

to 35

floppy drive)

Model 30 Mode

Bits 7 6 of ASC register are 00 This

mode supports the PS2 Model 30 configuration and regis-

ter set The DMA enable bit in the Digital Output Register

becomes valid (IRQ6 and DRQ can be TRI-STATE) TC is

active high and DENSEL becomes active low (default to

floppy drive)

53 CONTROLLER PHASES

The FDC has three separate phases of a command the

Command Phase the Execution Phase and the Result

Phase Each of these controller phases determine how data

is transferred between the floppy controller and the host

microprocessor In addition when no command is in prog-

ress the controller is in the Idle Phase or Drive Polling

Phase

531 Command Phase

During the Command Phase the mP writes a series of bytes

to the Data Register The first command byte contains the

opcode for the command and the controller knows how

many more bytes to expect based on this opcode byte The

remaining command bytes contain the particular parameters

required for the command The number of command bytes

varies for each particular command All the command bytes

must be written in the order specified in the Command De-

scription Table The Execution Phase starts immediately af-

ter the last byte in the Command Phase is written Prior to

performing the Command Phase the Digital Output Register

should be set and the data rate should be set with the Data

Rate Select Register or Configuration Control Register

The Main Status Register controls the flow of command

bytes and must be polled by the software before writing

each Command Phase byte to the Data Register Prior to

writing a command byte the RQM bit (D7) must be set and

the DIO bit (D6) must be cleared in the MSR After the first

command byte is written to the Data Register the CMD

PROG bit (D4) is also set and remains set until the last

Result Phase byte is read If there is no Result Phase the

CMD PROG bit will be cleared after the last command byte

is written

A new command may be initiated after reading all the result

bytes from the previous command If the next command

requires selecting a different drive or changing the data rate

the DOR and DSR or CCR should be updated If the com-

mand is the last command the software should deselect the

drive

Note

As a general rule the operation of the controller core is independent

of how the mP updates the DOR DSR and CCR The software must

ensure that the manipulation of these registers is coordinated with the

controller operation

532 Execution Phase

During the Execution Phase the disk controller performs

the desired command Commands that involve data trans-

fers (eg read write or format operation) require the mPto

write or read data to or from the Data Register at this time

Some commands such as a Seek or Recalibrate control the

readwrite head movement on the disk drive during the Exe-

cution Phase via the disk interface signals Execution of oth-

er commands does not involve any action by the mP or disk

drive and consists of an internal operation by the controller

PC87303 Datasheet(PDF) 57 Page - National Semiconductor (TI)

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