PC87303 datasheet(60/114 Pages) NSC

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50 FDC Functional Description (Continued)

535 Drive Polling Phase

The National FDC supports the polling mode of the old gen-

eration 8-inch drives as a means of monitoring any change

in status for each disk drive present in the system This

mode is supported for the sole purpose of providing back-

ward compatibility with software that expects its presence

While in the Idle Phase the controller enters a Drive Polling

Phase every 1 ms (based on the 500 kbps data rate) While

in the Drive Polling Phase the controller interrogates the

Ready Changed status for each of the four logical drives

The internal Ready line for each drive is toggled only after a

hardware or software reset and an interrupt is generated for

drive 0 At this point the software must issue four Sense

Interrupt commands to clear the Ready Changed State

status for each drive This requirement can be eliminated if

drive polling is disabled via the POLL bit in the Configure

command The Configure command must be issued within

500 ms (worst case ) of the hardware or software reset for

drive polling to be disabled

Even if drive polling is disabled drive stepping and delayed

power-down occurs in the Drive Polling Phase The control-

ler checks the status of each drive and if necessary it issues

a step pulse on the STEP output with the DIR signal at the

appropriate logic level Also the controller uses the Drive

Polling Phase to control the Automatic Low Power mode

When the Motor Off time has expired the controller waits

512 ms based on the 500 kbps and 1 Mbps data rate before

powering down if this function is enabled via the Mode com-

mand

If a new command is issued when the FDC is in the middle

of a polling routine the MSR will not indicate a ready status

for the next parameter byte until the poling sequence com-

pletes the loop This can cause a delay between the first

and second bytes of up to 500 ms at 250 kbps

54 DATA SEPARATOR

The internal data separator consists of an analog PLL and

its associated circuitry The PLL synchronizes the raw data

signal read from the disk drive The synchronized signal is

used to separate the encoded clock and data pulses The

data pulses are deserialized into bytes and then sent to the

P by the controller

The main PLL consists of five main components a phase

comparator a charge pump a filter a voltage controlled

oscillator (VCO) and a programmable divider The phase

comparator detects the difference between the phase of the

divider’s output and the phase of the raw data being read

from the disk This phase difference is converted to a cur-

rent by the charge pump which either charges or discharg-

es one of three filters which is selected based on the data

rate The resulting voltage on the filter changes the frequen-

cy of the VCO and the divider output to reduce the phase

difference between the input data and the divider’s output

The PLL is ‘‘locked’’ when the frequency of the divider is

exactly the same as the average frequency of the data read

from the disk A block diagram of the data separator is

shown in

Figure 5-1

To ensure optimal performance the data separator incorpo-

rates several additional circuits The quarter period delay

line is used to determine the center of each bit cell and to

disable the phase comparator when the raw data signal is

missing a clock or data pulse in the MFM or FM pattern A

secondary PLL is used to automatically calibrate the quarter

period delay line The secondary PLL also calibrates the

center frequency of the VCO

To eliminate the logic associated with controlling multiple

data rates the FDC supports each of the four data rates

(250 300 500 kbps and 1 Mbps) with a separate optimized

internal filter The appropriate filter for each data rate is au-

tomatically switched into the data separator circuit when the

data rate is selected via the Data Rate Select or Configura-

tion Control Register These filters have been optimized

through lab experimentation and are designed into the con-

troller to reduce the external component cost associated

with the floppy controller

The FDC has a dynamic window margin and lock range per-

formance capable of handling a wide range of floppy disk

drives Also the data separator works well under a variety of

conditions including the high motor speed fluctuations of

floppy compatible tape drives

Figure 5-2 shows the floppy disk controller dynamic window

margin performance at the four different data rates Dynam-

ic window margin is the primary indicator of the quality and

performance level of the data separator This measurement

indicates how much motor speed variation (MSV) of the

drive spindle motor and bit jitter (or window margin) can be

tolerated by the data separator

MSV is shown on the x-axis of the dynamic window margin

graph MSV is translated directly to the actual data rate of

the data as it is read from the disk by the data separator

That is a faster than nominal motor will result in a higher

frequency in the actual data rate

The dynamic window margin performance curves also indi-

cate how much bit jitter (or window margin) can be tolerated

by the data separator This parameter is shown on the

y-axis of the graphs Bit jitter is caused by the magnetic

interaction of adjacent data pulses on the disk which effec-

tively shifts the bits away from their nominal positions in the

middle of the bit window Window margin is commonly mea-

sured as a percentage This percentage indicates how far a

data bit can be shifted early or late with respect to its nomi-

nal bit position and still be read correctly by the data sepa-

rator If the data separator cannot correctly decode a shifted

bit then the data is misread and a CRC results

PC87303 Datasheet(PDF) 60 Page - National Semiconductor (TI)

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