PC87303 datasheet(29/114 Pages) NSC

29 / 114 page

30 FDC Register Description (Continued)

Motor Enable 0

Active high status of the MTR0

disk interface output Low after a hardware reset

unaffected by a software reset

SRBModel 30 Mode

DESC

DRV2

DR1

DR0

WDATA

RDATA

WGATE

DR3

DR2

RESET

COND

2nd Drive Installed

Active low status of the

DRV2 disk interface input

Drive Select 1

Active low status of the DR1 disk

interface output

Drive Select 0

Active low status of the DR0 disk

interface output

Write Data

Active high status of latched WDATA

signal This bit is latched by the inactive going edge

of WDATA and is cleared by a read from the DIR

This bit is not gated by WGATE

Read Data

Active high status of latched RDATA

signal It is latched by the active going edge of

RDATA and is cleared by a read from the DIR

Write Gate

Active high status of latched WGATE

signal This bit is latched by the active going edge of

WGATE and is cleared by a read from the DIR

Drive Select 3

Active low status of the DR3 disk

interface output

Note

The MTR3 MTR2 DRV3 DRV2 pins are only available in

four-drive mode (bit 4 of FER is 1) and require external

logic

Drive Select 2

Active low status of the DR2 disk

interface output

Note

The MTR3 MTR2 DRV3 DRV2 pins are only available in

four-drive mode (bit 4 of FER is 1) and require external

logic

313 Digital Output Register (DOR)

ReadWrite

The DOR controls the drive select and motor enable disk

interface outputs enables the DMA logic and contains a

software reset bit The contents of the DOR is set to 00

(hex) after a hardware reset and is unaffected by a software

reset The DOR can be written to at any time

DOR

DESC

MTR3 MTR2 MTR1 MTR0 DMAEN RESET

DRIVE DRIVE

SEL 1

SEL 0

RESET

0000

COND

Motor Enable 3

This bit controls the MTR3 disk

interface output A1in this bit causes the MTR3 pin

to go active

Motor Enable 2

Same function as D7 except for

MTR2

Motor Enable 1

Same function as D7 except for

MTR1 (See bit 4 of FCR for further information)

Motor Enable 0

Same function as D7 except for

MTR0 (See bit 4 of FCR for further information)

DMA Enable

This bit has two modes of operation

PC-AT mode or Model 30 mode

Writinga1to this

bit enables the FDRQ FDACK TC and IRQ6 pins

Writinga0to this bit disables the FDACK and TC

pins and TRI-STATE the FDRQ and the IRQ6 pins

This bit is a 0 after a reset when in these modes

PS2 mode

This bit is reserved and the FDRQ

FDACK TC and IRQ6 pins are always enabled Dur-

ing a reset the FDRQ FDACK TC and IRQ6 lines

remain enabled and D3 is 0

Reset Controller

Writinga0to this bit resets the

controller It remains in the reset condition until a 1

is written to this bit A software reset does not affect

the DSR CCR and other bits of the DOR A soft-

ware reset affects the Configure and Mode com-

mand bits (see Section 40 FDC Command Set De-

scription) The minimum time that this bit must be

low is 100 ns Thus toggling the Reset Controller bit

during consecutive writes to the DOR is an accept-

able method of issuing a software reset

D1 D0 Drive Select

These two bits are binary encoded for

the four drive selects DR0 – DR3 so that only one

drive select output is active at a time (See bit 4 of

FCR for further information)

It is common programming practice to enable both the mo-

tor enable and drive select outputs for a particular drive

Table 3-2 below shows the DOR values to enable each of

the four drives

TABLE 3-2 Drive Enable Values

Drive

DOR Value

1Ch

12D

24E

38F

Note

The MTR3 MTR2 DRV3 DRV2 pins are only available in four-drive

mode (bit 4 of FER is 1) and require external logic

314 Tape Drive Register (TDR)

ReadWrite

The TDR register is the Tape Drive Register and the floppy

disk controller media and drive type register The register

has three modes of operation (see Table 3-3)

Compatible PC-AT TDR mode

The register is used to as-

sign a particular drive number to the tape drive support

mode of the data separator All other logical drives can be

assigned as floppy drive support Bits 2 – 7 are TRI-STATE

during read

Automatic Media Sense mode

Bits 5 – 7 are implemented

in addition to the bits of the Compatible PC-AT TDR mode

Bits 2 – 4 are reserved

Enhanced mode

This is the PS2 TDR mode It uses all

the register’s bits for operation with PS2 floppy drives

The use of the TDR bits for each of these modes is shown

in Table 3-3

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