PC87303 datasheet(92/114 Pages) NSC

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90 Keyboard Controller and Real-Time Clock (Continued)

Rext e 5kX

C1 e 12

x 15 pF

C2 e 15 pF

Cparasitic e 0

x 8pF

TLC12074 – 49

FIGURE 9-13 Oscillator Internal and External Circuitry

The start-up time of this oscillator may vary from two to

seven seconds and is due to the high ‘‘Q’’ of the crystal

The parameters below describe the crystal to be used

Parallel Resonant tuning fork (N cut) or XY Bar

Q l 35k

Load Capacitance (CL)

9 pF to 13 pF

Accuracy

User Choice

Temperature Coefficient

User Choice

924 Time Keeping

The time is kept in BCD or binary format The format is

determined by bit 2 of Control Register B (DM) Either 12 or

24 hour representation for the hours can be maintained as

determined by bit 1 of Control Register B (2412) Note that

when changing the format the time registers must be re-ini-

tialized to the corresponding data format

Daylight savings and leap year exceptions are handled by

the time keeping function When bit 0 of Control Register A

(DSE) is a ‘‘1’’ time advances from 15959 AM to 30000

on the first Sunday in April On the last Sunday of October

time changes from 15959 to 10000 when daylight savings

is enabled On leap year February is extended to 29 days

The time is updated once per second If a read of the timing

registers coincides with an update data read may not be

valid Also writes to time registers during an update have

undefined results

To avoid accessing invalid data the RTC in the PC87303

provides a user copy of the time registers Then four meth-

ods are available for reading and writing time to ensure that

the correct time is written or read They are as follows

Method 1

Set the SET bit (CRB7)

Set the SET bit to 1 This takes a snapshot of the internal

time registers and loads it into the user copy Then when

the SET bit is written with 0 the user copy will update the

internal registers

Method 2

Access after detection of an Update Ended

Interrupt

This interrupt indicates that an update has just completed

and the next update will occur after 999 ms

Method 3

Poll update-in-progress (bit 7 in Control Reg-

ister A)

The update occurs 244 ms after the update-in-progress

bit goes high Therefore ifa0is read there is a minimum

of 244 ms in which the time is guaranteed to remain sta-

ble

Method 4

Use a Periodic interrupt to determine if an

update cycle is in progress

The periodic interrupt is first set to a desired period The

program can then use the periodic interrupt to signify that

there is (Periodic Interrupt2 a 244 ms) remaining until

another update occurs

The Alarm condition is also generated by the Time Keeping

function After each update the seconds minutes and

hours are compared with the seconds alarm minutes alarm

and hours alarm If equal the Alarm lag is set in Control

TLC12074 – 52

where

UIP eUpdate In Progress Bit

UF e Update Ended Flag (Update Ended Interrupt if Enabled)

PF e Periodic Flag (Periodic Interrupt if Enabled)

AF e Alarm Flag (Alarm Interrupt if Enabled)

Flags (and IRQ) are reset at the conclusion of Control Register C read or by RESETC low

A e

Update in Progress Bit High before Update Occurs e 244 ms

B e

Periodic interrupt to Update e P2 a 244 ms

C e

Update to Alarm Interrupt e 305 ms

P e

Period is programmed by RS3–0 of control Register A

FIGURE 9-14 InterruptStatus Timing

PC87303 Datasheet(PDF) 92 Page - National Semiconductor (TI)

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