PC87303 datasheet(15/114 Pages) NSC

15 / 114 page

10 Pin Description (Continued)

TABLE 1-1 Pin Descriptions (Alphabetical)

(Continued)

Symbol

Function

TRK0

Track 0

This input indicates to the controller that the head of the selected floppy disk drive is at

track zero

VBAT

Battery

Real-Time Clock battery pin

VDD

1 17

Digital Supply

This is the 5V supply voltage for the digital circuitry

41 57

79 101

121 140

150

VDDA

Analog Supply

This pin is the 5V supply for the analog data separator

VLD01

87 98

Valid Data

These inputs are sensed during reset and determine the state of bit 5 in the FDC Tape

Drive Register (3F3h) Thus they determine whether bits 6 and 7 of this register contain valid media

id information for floppy drives 0 and 1 If VLD0 is sensed low at reset then whenever drive 0 is

accessed bit 5 of the Tape Drive Register is a 0 indicating that bits 6 and 7 contain valid media id

information If VLD0 is sensed high at reset then whenever drive 0 is accessed bit 5 of the Tape

Drive Register is a 1 indicating that bits 6 and 7 do not contain valid media id information The same

is true of VLD1 relative to the media id information for drive 1

If bit 0 of FCR is 1 the VLD bits have no meaning VLD0 value during reset is loaded into bit 0 of FCR

(to select between media sense or DRATE) A 30 kX internal pulldown resistor is present on each

pin Use a 10 kX resistor to pull these pins high during reset These strap option pins are CMOS input

buffers (See IDEHI DRID1 and DTR2 for further information)

VSSA

Analog Ground

This is the analog ground for the data separator

VSS

7 11

Digital Ground

This is the ground for the digital circuitry

32 40

58 70

71 80

81 92

102 115

120 130

136 139

149 160

WAIT

124

Wait

This signal is used in EPP mode by the parallel port device to extend its access cycle It is

active low (See BUSY and Table 7-5 for further information)

Write

Active low input to signal to indicate a write from the microprocessor to the controller

WDATA

Write Data

This output is the write precompensated serial data that is written to the selected floppy

disk drive Precompensation is software selectable

WGATE

Write Gate

This output signal enables the write circuitry of the selected disk drive WGATE has been

designed to prevent glitches during power up and power-down This prevents writing to the disk when

power is cycled

Write Protect

This input indicates that the floppy disk in the selected drive is write protected

WRITE

135

Write Strobe

This signal is used in EPP mode as a write strobe It is active low (See STB and Table

7-5 for further information)

X1OSC

Crystal1Clock

One side of an external 24 MHz crystal is attached here The other side is

connected to X2 If a crystal is not used a TTL or CMOS compatible clock is connected to this pin

X1C

Crystal1 Slow

Input for the internal Real-Time Clock crystal oscillator amplifier

X2C

Crystal2 Slow

Output for the internal Real-Time Clock crystal oscillator amplifier

Crystal2

One side of an external 24 MHz crystal is attached here The other side is connected to

X1OSC This pin is left unconnected if an external clock is used

ZWS

Zero Wait State

This pin is the Zero Wait State open drain output pin ZWS is driven low when the

EPP or the ECP is written and the access can be shortened

PC87303 Datasheet(PDF) 15 Page - National Semiconductor (TI)

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