VT6516 datasheet(3/73 Pages) ETC

3 / 73 page

VIA Technologies, Inc.

Preliminary VT6516 Datasheet

TABLE OF CONTENTS

TABLE OF CONTENTS ................................................................................................................................ 3

FIGURES AND TABLES ............................................................................................................................... 4

REVERSION HISTORY ................................................................................................................................ 5

FEATURES ................................................................................................................................................ 6

BLOCK DIAGRAM...................................................................................................................................... 9

BALL OUT DIAGRAM ............................................................................................................................... 11

RMII-mode Ball out Diagram ........................................................................................................... 11

MII-mode Ballout Diagram............................................................................................................... 12

LOGIC SYMBOL ...................................................................................................................................... 13

PIN DESCRIPTIONS .................................................................................................................................. 14

JUMPER STRAPPING................................................................................................................................. 18

SECTION I FUNCTIONAL DESCRIPTIONS...................................................................................... 19

1. GENERAL DESCRIPTION ...................................................................................................................... 19

2. THE VIA ETHER SWITCH ARCHITECTURE............................................................................................ 19

2.1 Switch initialization procedures .................................................................................................. 19

2.2 Packet receiving and forwarding follow .......................................¿ ù

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3. INTERFACE DESCRIPTIONS................................................................................................................... 20

3.1 Buffer Memory (SDRAM) Interface and Table (SRAM) interface..¿ ù

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4. FUNCTIONAL DESCRIPTION ................................................................................................................. 33

4.1 Packet Reception and Address recognition.................................................................................. 33

4.2 Packet Forwarding and VLAN..................................................................................................... 33

4.3 Network Management Features ................................................................................................... 34

SECTION II REGISTER MAP ............................................................................................................... 36

1. REGISTER TABLES ............................................................................................................................. 36

2 CPU INTERFACE REGISTERS MAP......................................................................................................... 36

3 SWITCH INTERNAL REGISTERS MAP..................................................................................................... 37

4. DETAIL OF SWITCH REGISTER.............................................................................................................. 44

4.1 Registers of SDRAM Control Module......................................................................................... 44

4.2 Registers of SRAM Control Module............................................................................................ 46

4.4 Registers of Buffer Control Module............................................................................................. 48

4.5 Registers of Forwarding Control Module ................................................................................... 49

4.6 Registers of PHY Control Module .............................................................................................. 53

4.7 Registers of EEPROM Control Module ....................................................................................... 55

4.8 Registers of CPU Interface Module............................................................................................. 56

4.9 Registers of MAC/IO Control Module ......................................................................................... 59

4.10 Registers of CPU IO Control Module ....................................................................................... 63

SECTION III ELECTRICAL SPECIFICATIONS................................................................................. 65

ABSOLUTE MAXIMUM RATINGS............................................................................................................... 65

DC CHARACTERISTICS............................................................................................................................ 65

AC CHARACTERISTICS............................................................................................................................ 65

PACKAGE MECHANICAL SPECIFICATIONS ................................................................................................. 73

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