VT6516 datasheet(44/73 Pages) ETC

44 / 73 page

VIA Technologies, Inc.

Preliminary VT6516 Datarsheet

-44-

5000H

MAC & I/O Control Module of Port

as same as Port 0

5400H

MAC & I/O Control Module of Port

as same as Port 0

5800H

MAC & I/O Control Module of Port

as same as Port 0

5C00H

MAC & I/O Control Module of Port

as same as Port 0

6000H

MAC & I/O Control Module of Port

as same as Port 0

6400H

CPU IO Control Module

00H

CPU packet read byte count register bits

[7:0]

PKT_BYTE_C

[7:0] 0

R/O

01H

CPU packet read byte count register bits

[10:8]

PKT_BYTE_C

[10:8

]

R/O

02H

CPU packet read status register

RD_PKT_STA

TUS

[1:0] 0

R/O

03H

Packet source port ID

PKT_SRC_PO

[3:0] 0

R/O

04H

CPU IO port configuration register

CPUIO_CFG

[1:0] 0

10H

CPU packet write status register

WR_PKT_STA

TUS

[2:0] 0

R/O

4. DETAIL OF SWITCH REGISTER

4.1 Registers of SDRAM Control Module

* Base Address: 0000H

Addres

(offset

)

Function

Name

Bits

Defau

Value

00H

SDRAM TYPE:

0: 16Mbit SDRAM chip (default)

1: 64Mbit

This register has to be specified before initialization of the buffer

control because the Bank 1 free buffer pointer should have initial

value 130 for 16Mbit SDRAM, or, initial value 131 for 64Mbit

SDRAM.

SDRAMTYPE [0]

R/W

01H

CAS Latency for read operation:

2’b00: latency 1

2’b01: latency 2

2’b10: latency 3 (default)

This latency specifies the required delay between the CAS cycle and

the first read cycle. Note that the CAS latency has to be specified

before using RSDM in SDRAM initialization.

[1:0]

R/W

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