VT6516 datasheet(20/73 Pages) ETC

20 / 73 page

VIA Technologies, Inc.

Preliminary VT6516 Datarsheet

-20-

2. When receive MAC (RMAC) receives a packet data from the network interface – either through MII or

reduced MII (RMII) – it packs the data into 16-bit word then passes it to input control. If RMAC detects any

error, it also notifies input control to stop forwarding process.

3. Input control extracts the destination MAC address from incoming data, passes it along to forwarding table

control for forwarding decision. In the mean while, it packs 16-bit words into 64-bit quad-words, and saves

it to an input FIFO before storing the packet data to SDRAM.

4. If the switch is configured to “store and forward” mode, input control queues the packet to the output queue

of the destination port after input control is informed by RMAC that this is a good packet and it stores all

packet data to SDRAM. If the switch is configured to “cut-through” mode, the input control queues the

packet to the output queue of the destination port after enough amount of packet is stored in SDRAM to

prevent output FIFO under-run.

5. After the whole packet is received and FCS is correct, input control pass the source MAC address of the

packet to forwarding table control for address learning.

6. Output control of the outbound port de-queue the packet from output queue, and fetch packet data from

SDRAM and save it into output FIFO. Then it notifies the transmit MAC (TMAC) of the new packet to

transmit.

7. TMAC grabs 16-bit at a time from output control, adds preamble and SFD to the beginning of the packet,

then send them out. Proper deferring is done if necessary to conform to 802.3 standard.

8. After the packet is successfully transmitted, TMAC notifies output control of the successful transmission.

Output control then returns the packet to buffer pool.

3. INTERFACE DESCRIPTIONS

BUFFER MEMORY (SDRAM) INTERFACE AND TABLE (SSRAM) INTERFACE

VT6516 provides a 64-bit SDRAM/SGRAM interface for packet buffering and a 32-bit synchronous SRAM

(SSRAM) interface for maintaining address table and various link lists. VT6516 uses SDRAM as packet buffers.

Each packet buffer is a 1536-byte contiguous memory block in SDRAM, and corresponds to a 12-byte link node

data structure in SSRAM. Except the first 128 link nodes, each link node can be part of an output queue, a free

buffer link list, or held in input or output control. The first 128 link nodes are divided into 16 groups, each

pre-assigned to a specific input control, and bit-mapped inside buffer control for faster allocate/free operation

and reduce SSRAM usage.

Initially, each input port control would request one packet buffer from its private buffer pool. Each time

when a packet buffer is consumed by an incoming packet, the input port control will request another packet

buffer to prepare for next packet. The common shared packet memory will be allocated only when there’s no

free permanent packet memory for that port. See Figure 3-4.

VT6516 Datasheet(PDF) 20 Page - List of Unclassifed Manufacturers