VT6516 datasheet(18/73 Pages) ETC

18 / 73 page

VIA Technologies, Inc.

Preliminary VT6516 Datarsheet

-18-

RMII interface

See Ball

Table

CRS_DV[15:0

]

Carries sense and data valid from port 15 to port 0 :

See Ball

Table

RXD0[15:0]

Receive data zero from port 15 to port 0 :

See Ball

Table

RXD1[15:0]

Receive data one from port 15 to port 0 :

See Ball

Table

TXEN[15:0]

Transmit enable from port 15 to port 0 :

See Ball

Table

TXD0[15:0]

Transmit data zero from port 15 to port 0 :

See Ball

Table

TXD1[15:0]

Transmit data one from port 15 to port 0 :

Power Supply & Ground

See Ball

Table

VDD, VDDA

Positive 3.3V Supply: Supply power to Internal digital logic, Digital I/O

pads, and TD, TX pads. Double bonding may be required.

See Ball

Table

VSS, VSSA

Negative Supply: digital ground. Multiple bonding pads are required to

separate core and I/O pads ground.

JUMPER STRAPPING

Jumper

Description

HOST Clock

J1 [5-6], [3-4], [1-

SYSLED[3:

HOST Clock (HCLK) Rate Selection:

J1[OFF,OFF,OFF] (SYSLED[3:1]==3’b111)

=> 8MHz

J1[ OFF,OFF, ON] (SYSLED[3:1]==3’b110)

=> 16MHz

J1[OFF, ON, OFF] (SYSLED[3:1]==3’b101)

=> 25MHz

J1[OFF, ON, ON] (SYSLED[3:1]==3’b100)

=> 4MHz

J1[ ON,OFF,OFF] (SYSLED[3:1]==3’b011)

=> 33MHz

PHY Mode

J1 [7-8]

SYSLED[4] PHY Device Selection:

J1[OFF] (SYSLED[4]==1’b1)

=> RMII PHY

J1[ ON] (SYSLED[3:1]==1’b0)

=> MII PHY

SRAM Type

J1 [11-12,9-10]

SYSLED[6:

SRAM Device Type Selection:

J1[OFF,OFF] (SYSLED[6:5]==2’b11)

=> 64K x 32 SRAM

J1[OFF,ON] (SYSLED[6:5]==2’b10)

=> 128K x 32 SRAM

J1[ON,OFF] (SYSLED[6:5]==2’b01)

=> 32K x 32 SRAM

VT6516 Datasheet(PDF) 18 Page - List of Unclassifed Manufacturers

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