VT6516 datasheet(17/73 Pages) ETC

17 / 73 page

VIA Technologies, Inc.

Preliminary VT6516 Datarsheet

-17-

See Ball

Table

TXD<3:0>[11:

Transmit Data for Port 0-11:

TXD is a bundle of 4 data signals (TXD<3:0>) that shall transition to the

TCLK. For each TCLK period in which TXEN is asserted, TXD<3:0> are

accepted for transmission by the PHY. TXD<0> is the least significant bit.

While TXEN is de-asserted, TXD<3:0> shall have no effect upon the

PHY, and the value of TXD<3:0> is unspecified.

See Ball

Table

TXEN[11:0]

Transmit Enable for Port 0-11:

TXEN shall transition synchronous to the TCLK. TXEN indicates the

nibbles presenting on the MII for transmission. It shall be asserted

synchronously with the first nibble of the preamble and shall remain

asserted while all nibbles to be transmitted are presented to the MII.

See Ball

Table

COL[11:0]

Collision Detected for Port 0-11:

COL shall be asserted by the PHY asynchronously upon detection of a

collision on the medium, and shall remain asserted while the collision

condition persists.

See Ball

Table

CRS[11:0]

Carrier Sense for Port 0-11:

CRS shall be asserted by the PHY asynchronously upon detection of a

non-idle medium or while TX_EN is asserted. CRS shall be de-asserted by

the PHY asynchronously upon detection of idle conditions on both

transmit and receive media. The PHY shall ensure that CRS remains

asserted throughout the duration of a collision condition.

See Ball

Table

RXD<3:0>[11

:0]

Receive Data for Port 0-11:

RXD is a bundle of 4 data signals (RXD<3:0>) that shall transition to the

RCLK. For each RCLK period in which RXDV is asserted, RXD<3:0>

from the PHY are accepted by the switch’s MAC. RXD<0> is the least

significant bit. While RXDV is de-asserted, RXD<3:0> shall have no

effect upon the switch’s MAC, and the value of RXD<3:0> is unspecified.

See Ball

Table

RCLK[11:0]

Receive Clock for Port 0-11:

RCLK is sourced from the PHY. RCLK is a continuous clock that provides

the timing reference for the transfer of the RXDV and RXD signals from

the PHY. A PHY operating at 100Mbps must provide a RCLK frequency

of 25MHz and a PHY operating at 10Mbps must provide a RCLK

frequency of 2.5MHz.

See Ball

Table

RXDV[11:0]

Receive Data Valid for Port 0-11:

RXDV is driven by the PHY to indicate the nibbles presenting on the MII

for receiving. RXDV shall transition synchronous to the RCLK. It shall be

asserted synchronously with the first nibble of the preamble and shall

remain asserted while all nibbles to be received are presented to the MII.

Note: Some flat MII input pin when the VT6516 under the RMII application, please use 22 ohm resister

pull down, refer to Table XXXX

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