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R5F564MFDDFB Datasheet(PDF) 128 Page - Renesas Technology Corp |
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R5F564MFDDFB Datasheet(HTML) 128 Page - Renesas Technology Corp |
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128 / 228 page  R01DS0173EJ0110 Rev.1.10 Page 128 of 228 Oct 24, 2016 RX64M Group 4. I/O Registers 000C 4810h EPTPC 0 SYNFP MAC Address Register SYMACRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4814h EPTPC 0 SYNFP MAC Address Register SYMACRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 481Ch EPTPC 0 SYNFP Local IP Address Register SYIPADDRR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4840h EPTPC 0 SYNFP Specification Version Setting Register SYSPVRR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4844h EPTPC 0 SYNFP Domain Number Setting Register SYDOMR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4850h EPTPC 0 Announce Message Flag Field Setting Register ANFR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4854h EPTPC 0 Sync Message Flag Field Setting Register SYNFR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4858h EPTPC 0 Delay_Req Message Flag Field Setting Register DYRQFR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 485Ch EPTPC 0 Delay_Resp Message Flag Field Setting Register DYRPFR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4860h EPTPC 0 SYNFP Local Clock ID Registers SYCIDRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4864h EPTPC 0 SYNFP Local Clock ID Registers SYCIDRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4868h EPTPC 0 SYNFP Local Port Number Register SYPNUMR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4880h EPTPC 0 SYNFP Register Value Load Directive Register SYRVLDR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4890h EPTPC 0 SYNFP Reception Filter Register 1 SYRFL1R 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4894h EPTPC 0 SYNFP Reception Filter Register 2 SYRFL2R 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4898h EPTPC 0 SYNFP Transmission Enable Register SYTRENR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48A0h EPTPC 0 Master Clock ID Register MTCIDU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48A4h EPTPC 0 Master Clock ID Register MTCIDL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48A8h EPTPC 0 Master Clock Port Number Register MTPID 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48C0h EPTPC 0 SYNFP Transmission Interval Setting Register SYTLIR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48C4h EPTPC 0 SYNFP Received logMessageInterval Value Indication Register SYRLIR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48C8h EPTPC 0 offsetFromMaster Value Register OFMRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48CCh EPTPC 0 offsetFromMaster Value Register OFMRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48D0h EPTPC 0 meanPathDelay Value Register MPDRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48D4h EPTPC 0 meanPathDelay Value Register MPDRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48E0h EPTPC 0 grandmasterPriority Field Setting Register GMPR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48E4h EPTPC 0 grandmasterClockQuality Field Setting Register GMCQR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48E8h EPTPC 0 grandmasterIdentity Field Setting Registers GMIDRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48ECh EPTPC 0 grandmasterIdentity Field Setting Registers GMIDRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48F0h EPTPC 0 currentUtcOffset/timeSource Field Setting Register CUOTSR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 48F4h EPTPC 0 stepsRemoved Field Setting Register SRR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC Table 4.1 List of I/O Registers (Address Order) (57 / 67) Address Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access Cycles Related Function ICLK PCLK ICLK PCLK |
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