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R5F564MFDDFB Datasheet(PDF) 130 Page - Renesas Technology Corp |
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R5F564MFDDFB Datasheet(HTML) 130 Page - Renesas Technology Corp |
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130 / 228 page  R01DS0173EJ0110 Rev.1.10 Page 130 of 228 Oct 24, 2016 RX64M Group 4. I/O Registers 000C 4C50h EPTPC 1 Announce Message Flag Field Setting Register ANFR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C54h EPTPC 1 Sync Message Flag Field Setting Register SYNFR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C58h EPTPC 1 Delay_Req Message Flag Field Setting Register DYRQFR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C5Ch EPTPC 1 Delay_Resp Message Flag Field Setting Register DYRPFR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C60h EPTPC 1 SYNFP Local Clock ID Registers SYCIDRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C64h EPTPC 1 SYNFP Local Clock ID Registers SYCIDRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C68h EPTPC 1 SYNFP Local Port Number Register SYPNUMR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C80h EPTPC 1 SYNFP Register Value Load Directive Register SYRVLDR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C90h EPTPC 1 SYNFP Reception Filter Register 1 SYRFL1R 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C94h EPTPC 1 SYNFP Reception Filter Register 2 SYRFL2R 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C98h EPTPC 1 SYNFP Transmission Enable Register SYTRENR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CA0h EPTPC 1 Master Clock ID Register MTCIDU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CA4h EPTPC 1 Master Clock ID Register MTCIDL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CA8h EPTPC 1 Master Clock Port Number Register MTPID 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CC0h EPTPC 1 SYNFP Transmission Interval Setting Register SYTLIR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CC4h EPTPC 1 SYNFP Received logMessageInterval Value Indication Register SYRLIR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CC8h EPTPC 1 offsetFromMaster Value Register OFMRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CCCh EPTPC 1 offsetFromMaster Value Register OFMRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CD0h EPTPC 1 meanPathDelay Value Register MPDRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CD4h EPTPC 1 meanPathDelay Value Register MPDRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CE0h EPTPC 1 grandmasterPriority Field Setting Register GMPR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CE4h EPTPC 1 grandmasterClockQuality Field Setting Register GMCQR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CE8h EPTPC 1 grandmasterIdentity Field Setting Registers GMIDRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CECh EPTPC 1 grandmasterIdentity Field Setting Registers GMIDRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CF0h EPTPC 1 currentUtcOffset/timeSource Field Setting Register CUOTSR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4CF4h EPTPC 1 stepsRemoved Field Setting Register SRR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4D00h EPTPC 1 PTP-primary Message Destination MAC Address Setting Registers PPMACRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4D04h EPTPC 1 PTP-primary Message Destination MAC Address Setting Registers PPMACRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4D08h EPTPC 1 PTP-pdelay Message MAC Address Setting Registers PDMACRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4D0Ch EPTPC 1 PTP-pdelay Message MAC Address Setting Registers PDMACRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4D10h EPTPC 1 PTP Message EtherType Setting Register PETYPER 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC Table 4.1 List of I/O Registers (Address Order) (59 / 67) Address Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access Cycles Related Function ICLK PCLK ICLK PCLK |
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