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R5F564MFDDFB Datasheet(PDF) 129 Page - Renesas Technology Corp |
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R5F564MFDDFB Datasheet(HTML) 129 Page - Renesas Technology Corp |
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129 / 228 page  R01DS0173EJ0110 Rev.1.10 Page 129 of 228 Oct 24, 2016 RX64M Group 4. I/O Registers 000C 4900h EPTPC 0 PTP-primary Message Destination MAC Address Setting Registers PPMACRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4904h EPTPC 0 PTP-primary Message Destination MAC Address Setting Registers PPMACRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4908h EPTPC 0 PTP-pdelay Message MAC Address Setting Registers PDMACRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 490Ch EPTPC 0 PTP-pdelay Message MAC Address Setting Registers PDMACRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4910h EPTPC 0 PTP Message EtherType Setting Register PETYPER 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4920h EPTPC 0 PTP-primary Message Destination IP Address Setting Register PPIPR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4924h EPTPC 0 PTP-pdelay Message Destination IP Address Setting Register PDIPR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4928h EPTPC 0 PTP event Message TOS Setting Register PETOSR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 492Ch EPTPC 0 PTP general Message TOS Setting Register PGTOSR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4930h EPTPC 0 PTP-primary Message TTL Setting Register PPTTLR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4934h EPTPC 0 PTP-pdelay Message TTL Setting Register PDTTLR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4938h EPTPC 0 PTP event Message UDP Destination Port Number Setting Register PEUDPR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 493Ch EPTPC 0 PTP general Message UDP Destination Port Number Setting Register PGUDPR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4940h EPTPC 0 Frame Reception Filter Setting Register FFLTR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4960h EPTPC 0 Frame Reception Filter MAC Address 0 Setting Registers FMAC0RU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4964h EPTPC 0 Frame Reception Filter MAC Address 0 Setting Registers FMAC0RL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4968h EPTPC 0 Frame Reception Filter MAC Address 1 Setting Registers FMAC1RU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 496Ch EPTPC 0 Frame Reception Filter MAC Address 1 Setting Registers FMAC1RL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 49C0h EPTPC 0 Asymmetric Delay Setting Register DASYMRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 49C4h EPTPC 0 Asymmetric Delay Setting Register DASYMRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 49C8h EPTPC 0 Timestamp Latency Setting Register TSLATR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 49CCh EPTPC 0 SYNFP Operation Setting Register SYCONFR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 49D0h EPTPC 0 SYNFP Frame Format Setting Register SYFORMR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 49D4h EPTPC 0 Response Message Reception Timeout Register RSTOUTR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C00h EPTPC 1 SYNFP Status Register SYSR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C04h EPTPC 1 SYNFP Status Notification Permission Register SYIPR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C10h EPTPC 1 SYNFP MAC Address Registers SYMACRU 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C14h EPTPC 1 SYNFP MAC Address Registers SYMACRL 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C1Ch EPTPC 1 SYNFP Local IP Address Register SYIPADDRR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C40h EPTPC 1 SYNFP Specification Version Setting Register SYSPVRR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC 000C 4C44h EPTPC 1 SYNFP Domain Number Setting Register SYDOMR 32 32 9 to 211 PCLKA 2 to 106 ICLK EPTPC Table 4.1 List of I/O Registers (Address Order) (58 / 67) Address Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access Cycles Related Function ICLK PCLK ICLK PCLK |
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