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259481A Marking, TPS259481AYWPR Datasheet(PDF) 39 Page - Texas Instruments |
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TPS259481AYWPR Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 56 page ![]() When the bus voltages (IN1 and IN2) are matched, device in each path sees a forward voltage drop and is ON delivering the load current. During this period, current is shared between the rails in the ratio of differential voltage drop across each device. In addition to supply ORing, the devices protect the system from overvoltage, excessive inrush current, overload and short-circuit faults at all times. Note ORing can be done either between two similar rails or between dissimilar rails. For ORing cases with skewed voltage combinations, the dVdt pin capacitor rating should be chosen based on the highest of the 2 supplies. Refer to Recommended Operating Conditions table for more details. 9.5 Priority Power MUXing Applications having two energy sources such as PCIe cards, Tablets and Portable battery powered equipment require preference of one source to another. For example, mains power (wall-adapter) has the priority over the internal battery back-up power. These applications demand for switchover from mains power to backup power only when main input voltage falls below a user defined threshold. The TPS25948xx devices provide a simple solution for priority power multiplexing needs. Figure 9-14 shows a typical priority power multiplexing implementation using TPS259480x devices. When primary (priority) power source (IN1) is present and within the valid range (not in UV/OV condition), the primary path device path powers the OUT bus irrespective of whether auxiliary supply voltage (VIN2) is greater than, equal to or less than primary supply voltage (VIN1). The device in auxiliary path is held in off condition by forcing its OVLO pin to high using the SPLYGD signal from the primary path device. Once the primary supply voltage falls outside the user-defined valid operating range (UV/OV condition), the primary path device de-asserts the SPLYGD which signals the auxiliary path device to turn on and the system starts operating from the auxiliary supply. During this transition, the auxiliary path device bypasses its dVdt limited startup and performs a fast recovery to start delivering power within tSWOV. When the primary supply is restored, the primary path device turns on fully at a defined slew rate and then asserts its SPLYGD pin high to turn the auxiliary path device off, allowing a seamless transition from auxiliary to the primary supply with minimal output voltage droop and with no shoot-through current. A key consideration in power MUXing applications is the minimum voltage the output bus droops to during the switchover from one supply to another. This in turn depends on multiple factors including the output load current (ILOAD), output bus hold-up capacitance (COUT) and switchover time (tSW). While switching from primary supply (VIN1) to auxiliary supply (VIN2), the minimum bus voltage can be calculated using Equation 15. Here, the switchover time (tSW) is equal to the fast OVLO recovery time (tSWOV) taken by the TPS259480x variants to turn on fully and start delivering current to the load. VOUT,min (V) = min (VIN1, VIN2) ‐ tSW (µs) × ILOAD (A) COUT (µF) (15) While switching from auxiliary supply (VIN2) to primary supply (VIN1), the minimum bus voltage can be calculated using Equation 16. Here the maximum switchover time is equal to the RCB recovery time (tSWRCB), depending on whether VIN1 is equal to or lower than VIN2 to start with. VOUT,min (V) = min (VIN1, VIN2) ‐ VFWDTH (V) ‐ tSWRCB (µs) × ILOAD (A) COUT (µF) (16) The SPLYGD pins of the devices can be used as a digital indication to identify which of the 2 supplies is active and delivering power to the load. www.ti.com TPS25948 SLVSGT9A – FEBRUARY 2023 – REVISED SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TPS25948 |
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