ADATE320 datasheet(65/83 Pages) AD

65 / 83 page

ADATE320

Data Sheet

Rev. B | Page 64 of 82

POWER SUPPLY SEQUENCING

The ADATE320 is designed to tolerate sequencing of power

supplies in any order. It is therefore not critical that the power

supplies be sequenced in any particular order; however, there

are recommended best practices.

The ADATE320 has two analog power supplies (VCC, VEE)

and one digital power supply (VDD). The analog supplies

service all of the analog functions on the chip such as level

setting DACs, driver, comparator, load, and PPMU. The digital

supply services the SPI and all digital CMOS control circuitry.

There is careful separation between the analog and digital partitions

of the chip, and significant effort has been made to decouple

these two partitions both functionally and electrically. The analog

partition remains in the default configuration in the absence of

VDD, and similarly, the digital partition remains in the default

configuration in the absence of either (or both) VCC and VEE.

It is not possible to guarantee predictable behavior of the analog

partition if either the VEE or VCC supply is poorly conditioned or

absent. It is therefore recommended that any externally connected

device be disconnected from the DUTx pin to prevent potential

damage to that device while either of the VEE or VCC supplies is

out of specification.

Assuming the VEE and VCC analog supplies are both applied and

within specification, the analog partition ensures that all functions

remain in the default configuration. This is true even when the

VDD supply is absent and digital CMOS control circuitry is not yet

functioning. In such a case (or whenever the RST pin is asserted),

all of the level setting DACs takes the voltage present at the

DUTGND input pin, and all SPI control bits assume their reset

default values. The analog functions remain in this safe condition

as long as VDD remains absent or as long as the RST pin remains

asserted.

It is recommended that the RST pin always be asserted during

the time that the VDD supply is being brought up. If this condition

is met, the level setting DACs continue to hold the DUTGND

potential after VDD stabilizes and after the RST pin is released. A

fully clocked reset sequence then initializes the level setting

DACs to the reset default conditions as specified in Table 29.

The reset sequence is described in more detail in the SPI Reset

Sequence and the Pin section.

In light of these considerations, it is recommended that the two

analog supplies be applied first. It is preferable that the smaller

valued supply (VEE) be applied before the larger valued supply

(VCC). Bring up the digital VDD supply next while the RST pin

is asserted. After VDD is stable and the RST pin is subsequently

released, a fully clocked reset sequence must follow. This power

supply sequence ensures that analog functions and all level

setting DACs receive the proper configuration information

during the digital partition reset sequence.

The power supplies must be removed in the reverse order.

Note that VREF and the high speed transmission line termination

pins (VTTDx, VTTCx) are all part of the analog partition, but they

are not treated as supplies. VREF can be managed independent of

VCC and VEE, provided its potential never goes outside those of

the VEE and VCC supply buses to prevent ESD protection diodes

from becoming forward biased. The VTTDx and VTTCx pins

do not have this restriction relative to VCC and VEE, but they

must never go outside the absolute maximum ratings as

measured with respect to PGND.

ADATE320 Datasheet(PDF) 65 Page - Analog Devices

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