ADATE320 datasheet(22/83 Pages) AD

22 / 83 page

Data Sheet

ADATE320

Rev. B | Page 21 of 82

Parameter

Symbol

Min

Typ

Max

Unit

Test

Level

Description

SDI to SCLK Setup

tDS

Setup time of SDI data prior to next rising edge of SCLK.

SDI to SCLK Hold

tDH

Hold time of SDI data following previous rising edge of SCLK.

SCLK to Valid SDO

tDO

Propagation delay from rising edge of SCLK to valid SDO data.

BUSY Assert from CS/RST

tBUSA

Propagation delay from first rising SCLK following valid CS release

(or RST release in the case of hardware reset) to BUSY assert.

BUSY Width

tBUSW

Following CS

Cycles

Delay time from first rising SCLK after valid CS release to BUSY

release. Satisfies the requirements detailed in the SPI Clock

Cycles and the Pin section, except following RST or software reset.

Following RST

744

Cycles

Delay time from first rising SCLK after RST release (or valid CS

release in the case of software reset) to BUSY release. Satisfies

the requirement of synchronous reset sequence detailed in the

SPI Clock Cycles and the Pin section.

BUSY Release from SCLK

tBUSR

Propagation delay from qualifying SCLK edge to BUSY release.

Width of RST Assert

tRMIN

Minimum width of asynchronous RST assert, 5 pF external loading.

RST to SCLK Setup at Assert

tRS

1.5

Minimum setup time of RST release to next rising edge of SCLK.

SCLK Cycles per SPI Word

tSPI

Cycles

Minimum number of SCLK rising edge cycles required per valid

SPI operation, including the minimum tCSAM requirement between

consecutive CS assertions.

Internal DAC Settling to

Within ±2 mV from

BUSY Release

tDAC

µs

Settling time of internal analog DAC levels to within ±2 mV.

Settling time is relative to the release of BUSY.1

The overall settling time may be dominated by the characteristics of an analog block (such as the PPMU or driver) and its respective mode setting (such as Range A or

Range B).

SPI TIMING DIAGRAMS

SCLK

SDI

D15 D14

SDO

BUSY

tCH

tCL

tCSAS

tCSAH

tCSO

tDS

tDH

tDO

tCSAM

tCSRS

tCSRH

tCSZ

tBUSA

tBUSR

tBUSW

NOTE 1

NOTES

1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE

FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE

SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS ACTIVE INDEPENDENT OF CS.

R/W

Figure 2. SPI Detailed Read/Write Timing Diagram

ADATE320 Datasheet(PDF) 22 Page - Analog Devices

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