DA9021 datasheet(47/142 Pages) DIALOG

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DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

47 of 142

A detection of a hard reset forces the assertion of nRESET to low when the sequencer returns from

POWERDOWN mode to RESET mode.

This type of reset is typically used only for severe or unrecoverable hardware or software problems,

because it completely resets the processor and can result in data loss.

11.4 Reset output (nRESET)

The nRESET signal is an active-low output signal from DA9021/22 to the host processor, which tells

the host to enter the hardware-reset state. nRESET is always asserted at the beginning of a

DA9021/22 cold start from NO-POWER mode and when the DA9021/22 returns to RESET mode.

nRESET can also be asserted as a soft reset after the sequencer finishes powering down without

progressing to RESET-mode.

The reset timer trigger signal can be configured to be EXT_WAKEUP, SYS_UP or PWR_UP. After

being asserted nRESET remains low until the reset timer is started from the selected trigger signal

and expires. The expiry time can be configured from 1 ms to 1024 ms.

11.5 System enable (SYS_EN)

SYS_EN is an input signal from the host processor to DA9021/22 (or can be default enabled via OTP

settings), which initiates enabling the system power supplies. The control SYS_EN will be initialised

from OTP if the related port is configured as GPI or GPO. The register bit SYS_EN can be read and

changed via the control interfaces. DA9021/22 will not accept any power mode transition commands

until the sequencer has stopped processing IDs. De-asserting SYS_EN informs the DA9021/22 that

the host processor is going into a standby/hibernate mode. When the port is changing from active to

passive state there is no IRQ or wakeup event trigger. With the exception of supplies that are

configured in ACTIVE mode with a voltage preset before powering down, all regulators and buck

converters in power domain POWER1, POWER and SYSTEM will be sequentially disabled in

reverse order.

11.6 Power enable (PWR_EN)

PWR_EN is an input signal from the host processor to DA9021/22 (or is configured via OTP or host

commands). Initialisation, IRQ assertion and register bit PWR_EN control is similar to SYS_EN. To

ensure the correct sequencing SYS_EN has to be active before asserting PWR_EN. When de-

asserting SYS_EN the sequencer will sequentially power down POWER1, POWER and SYSTEM

domains respectively.

11.7 Power1 enable (PWR1_EN)

PWR1_EN is an input signal from a host to DA9021/22 and is configured via OTP or host

commands. Initialisation, IRQ assertion and register bit PWR1_EN control is similar to SYS_EN. The

domain POWER1 is a sub power domain for general purpose.

11.8 General purpose feedback signal 1 (GP_FB1: EXT_WAKEUP/READY)

The feedback GP_FB1 supports two different modes. If configured as EXT_WAKEUP it is an active

high output signal to the host processor that indicates a valid wakeup event during POWERDOWN

mode. External signals that are causing wakeup events are debounced before DA9021/22 asserts

the EXT_WAKEUP signal. EXT_WAKEUP is released when entering the ACTIVE mode. If

configured as READY signal it indicates ongoing DVC or power sequencer activities. The signal is

active low and is asserted from DA9021/22 as long as the power sequencer processes IDs or DVC

voltage transitions are ongoing.

DA9021 Datasheet(PDF) 47 Page - Dialog Semiconductor

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