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PC87322VF Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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PC87322VF Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 84 page ![]() List of Tables TABLE 2-1 Default Configurations Controlled by Hardware 14 TABLE 2-2 Index and Data Register Optional Locations 15 TABLE 2-3 Encoded Drive and Motor Pin Information 16 TABLE 2-4 Primary and Secondary Drive Address Selection 16 TABLE 2-5 Parallel Port Addresses 17 TABLE 2-6 COM Port Selection for UART1 17 TABLE 2-7 COM Port Selection for UART2 17 TABLE 2-8 Address Selection for COM3 and COM4 17 TABLE 2-9 Logical Drive Exchange 18 TABLE 3-1 Register Description and Addresses 20 TABLE 3-2 Drive Enable Values 22 TABLE 3-3 Media ID Bit Functions 22 TABLE 3-4 Tape Drive Assignment Values 22 TABLE 3-5 Write Precompensation Delays 23 TABLE 3-6 Default Precompensation Delays 23 TABLE 3-7 Data Rate Select Encoding 24 TABLE 4-1 Typical Format Gap Length Values 33 TABLE 4-2 Typical Values for PC Compatible Diskette Media 33 TABLE 4-3 DENSEL Encoding 35 TABLE 4-4 DENSEL Default Encoding 35 TABLE 4-5 Effect of Drive Mode and Data Rate on Format and Write Commands 36 TABLE 4-6 Effect of GAP and WG on Format and Write Commands 36 TABLE 4-7 Sector Size Selection 36 TABLE 4-8 SK Effect on Read Data Command 37 TABLE 4-9 Result Phase Termination Values with No Error 37 TABLE 4-10 SK Effect on Read Deleted Data Command 38 TABLE 4-11 Maximum Recalibrate Step Pulses Based on R255 and ETR 38 TABLE 4-12 Scan Command Termination Values 39 TABLE 4-13 Status Register 0 Termination Codes 40 TABLE 4-14 Set Track Register Address 40 TABLE 4-15 Step Rate Time (SRT) Values 40 TABLE 4-16 Motor Off Time (MFT) Values 41 TABLE 4-17 Motor On Time (MNT) Values 41 TABLE 4-18 Verify Command Result Phase Table 42 TABLE 6-1 PC87322VF UART Register Addresses (AEN e 0) 50 TABLE 6-2 PC87322VF Register Summary for an Individual UART Channel 51 TABLE 6-3 PC87322VF UART Reset Configuration 52 TABLE 6-4 PC87322VF UART Divisors Baud Rates and Clock Frequencies 53 TABLE 6-5 PC87322VF Interrupt Control Functions 55 TABLE 7-1 Parallel Interface Register Addresses 56 TABLE 7-2 SPP Data Register Read and Write Modes 56 TABLE 7-3 Parallel Port Reset States 57 TABLE 7-4 EPP Registers 58 TABLE 7-5 Parallel Port Pin Out 61 TABLE 8-1 IDE Registers and Their ISA Addresses 62 TABLE 9-1 Nominal tICP tDRP Values 65 TABLE 9-2 Minimum tWDW Values 72 TABLE 10-1 PC87322VF Four Floppy Drive Encoding 77 4 |
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