PC87322VF datasheet(47/84 Pages) NSC

47 / 84 page

50 FDC Functional Description (Continued)

The FDC internal analog data separator has a much better

performance than comparable digital data separator de-

signs and does not require any external components

Note

The dynamic window margin curves were generated using a FlexStar

FS-540 Floppy Disk Simulator and a proprietary dynamic window mar-

gin test program written by National Semiconductor

The controller takes best advantage of the internal analog

data separator by implementing a sophisticated read algo-

rithm This ID search algorithm shown in

Figure 5-3 en-

hances the PLL’s lock characteristics by forcing the PLL to

relock to the crystal reference frequency any time the data

separator attempts to lock to a non-preamble pattern This

algorithm ensures that the PLL is not thrown way out of lock

by write splices or bad data fields

55 CRYSTAL OSCILLATOR

The FDC is clocked by a single 24 MHz signal An on-chip

oscillator is provided to enable the attachment of a crystal

or a clock signal

A parallel resonant crystal is preferred if at all possible In

some cases a series resonant crystal can be used but care

must be taken to ensure that the crystal does not oscillate

at a sub-harmonic frequency The oscillator is able to work

with high profile low profile and surface mount type crystal

enclosures External bypass capacitors (5 pF to 10 pF)

should be connected from XTAL1 and XTAL2 to GND If an

external oscillator circuit is used it must have a duty cycle of

at least 40% – 60% and minimum input levels of 24V and

250 kbs

TLC11870 – 12

300 kbs

TLC11870 – 13

500 kbs

TLC11870 – 14

1 Mbs

TLC11870 – 15

FIGURE 5-2 PC87322VF Dynamic Window Margin Performance

(Typical performance at VDD e 50V 25 C)

PC87322VF Datasheet(PDF) 47 Page - National Semiconductor (TI)