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PC87322VF Datasheet(PDF) 75 Page - National Semiconductor (TI) |
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PC87322VF Datasheet(HTML) 75 Page - National Semiconductor (TI) |
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75 / 84 page  90 Device Description (Continued) 9215 Enhanced Parallel Port Timing Symbol Parameter Conditions Min Max Units tWW WRITE Active from WR Active (Note 1) 45 ns tWST DSTRB or ASTRB Active from EPP 17 45 ns WR Active (Notes 1 2) EPP 19 65 ns tWEST DSTRB or ASTRB Active after EPP 17 0 ns WRITE Active EPP 19 10 ns tWPDh PD0 – 7 Hold after DSTRB or ASTRB Inactive 50 ns tHRW IOCHRDY Active after WAIT Active EPP 17 40 ns (Note 3) tWPDS PD0 – PD7 Valid after WRITE Active D0 – D7 is Stable 15 ns 15 ns before WR Active tEPDW 210 ns tEPDh 0ns tZWSa ZWS valid after WR or RD active 45 ns tZWSh ZWS hold after WR or RD inactive 0 ns Note 1 tWST and tWW are valid in EPP 19 only if WAIT is low when WR becomes active else tWST and tWW are measured from WAIT Note 2 The PC87322VF design guarantees that WRITE will not change from low to high before DSTRB or ASTRB goes from low to high Note 3 In EPP 19 IOCHRDY is measured from WR or RD TLC11870 – 47 FIGURE 9-17 Enhanced Parallel Port Timing 75 |
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