PC87322VF datasheet(10/84 Pages) NSC

10 / 84 page

10 Pin Description (Continued)

Symbol

Function

IRQ6

Interrupt 6

Active high output to signal the completion of the execution phase for certain FDC

commands Also used to signal when a data transfer is ready during a Non-DMA operation When in

PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS2 mode IRQ6 is

always enabled and bit D3 of the DOR is reserved

IRQ7

Interrupt 7

Active high output that indicates a parallel port interrupt When enabled this bit follows the

ACK signal input When bit 4 in the parallel port Control Register is set and the parallel port address is

designated as shown in Table 2-5 this interrupt is enabled When it is not enabled this signal is

TRI-STATE

Master Reset

Active high input that resets the controller to the idle state and resets all disk interface

outputs to their inactive states The DOR DSR CCR Mode command Configure command and Lock

command parameters are cleared to their default values The Specify command parameters are not

affected The Configuration Registers are set to their selected default values

MFM

During a chip reset when IDENT is low this pin is sampled to select the PS2 mode (MFM high)

or the Model 30 mode (MFM low) An internal pull-up or external pull-down 2 kX resistor selects

between the two PS2 modes When the PC-AT mode is desired (IDENT high) MFM should be left

pulled high internally MFM reflects the current data encoding format when RESET is inactive MFM e

high FM e low Defaults to low after a chip reset This signal can also be configured as the PUMP

data separator diagnostic output via the Mode command (see Section 426) (See IOCHRDY for

further information)

MTR01

46 43

Motor Select 01

These are the motor enable lines for drives 0 and 1 and are controlled by bits

D7 – D4 of the Digital Output register They are active low outputs They are encoded with information

to control four FDDs when bit 4 of the Function Enable Register (FER) is set MTR0 exchanges logical

motor values with MTR1 when bit 4 of FCR is set (See DR01 for more information)

Motor Select 1

This pin provides an additional Motor Select 1 signal in PPM Mode when PNFe0

This pin is the motor enable line for drive 1 when bit 4 of FCR is 0 It is the motor enable line for drive 0

when bit 4 of FCR is 1 This signal is active low (See BUSY and Table 7-5 for further information)

MSEN01

52 51

Media Sense

These pins are Media Sense input pins when bit 0 of FCR is 0 Each pin has a 10 kX

internal pull-up resistor When bit 0 of FCR is 1 these pins are Data Rate output pins and the pull-up

resistors are disabled (See DRATE01 for further information)

88 86

Media Sense

These pins provide additional Media Sense signals for PPM Mode and PNFe0 (See

PD5 7 and Table 7-5 for further information)

PD0 – 7

94 – 91

Parallel Port Data

These bidirectional pins transfer data to and from the peripheral data bus and the

parallel port Data Register These pins have high current drive capability (See DC Electrical

89–86

Characteristics) (See MSEN01 INDEX TRK0 WP RDATA DSKCHG and Table 7-5 for further

information)

PDIR

Parallel Port Direction

During reset the state of this pin determines the direction of the parallel port

data The direction is output (printer) when PDIR e 0 and PTR7e0 and it is input (scanner) when

PDIR e 1 and PTR7e0 An internal pull-down resistor of 30 kX is on each pin Use a 10 kX resistor

to pull this pin to high during reset

PWDN

Power-Down

This multi-function pin will stop the clocks andor the external crystal based on the

selections made in the Power and Test Register bits 1-2 (See CSOUT and ZWS for additional

information)

Paper End

This input is set high by the printer when it is out of paper This pin has a nominal 25 kX

pull-down resistor attached to it (See WDATA and Table 7-5 for further information)

POE

Parallel Port Output Enable

This pin is sensed during reset If it is low bit 7 of the Power and Test

is high then the direction of the parallel port data is determined by the state of the PDIR pin at reset

An internal pull-down resistor of 30 kX is on each pin Use a 10 kX resistor to pull this pin to high

during reset This strapping option may be overwritten using bit 7 of PTR

PNF

Printer Not Floppy

PNF is the Printer Not Floppy pin when bit 2 of FCR is 1 It selects the device

which is connected to the PPM pins A parallel printer is connected when PNF e 1 and a floppy disk

drive is connected when PNF e 0 This pin is the DRV2 input pin when bit 2 of FCR is 0 (See DRV2

for further information)

Read

Active low input to signal a data read by the microprocessor

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