PC87322VF datasheet(12/84 Pages) NSC

12 / 84 page

10 Pin Description (Continued)

Symbol

Function

WAIT

Wait

This signal is used in EPP mode by the parallel port device to extend its access cycle It is active

low (See BUSY and Table 7-5 for further information)

Write

Active low input to signal a write from the microprocessor to the controller

WDATA

Write Data

This output is the write precompensated serial data that is written to the selected floppy disk

drive Precompensation is software selectable

Write Data

This pin provides an additional Write Data signal in PPM Mode when PNF e 0 (See PE and

Table 7-5 for further information)

WGATE

Write Gate

This output signal enables the write circuitry of the selected disk drive WGATE has been

designed to prevent glitches during power-up and power-down This prevents writing to the disk when

power is cycled

Write Gate

This pin provides an additional Write Gate signal in PPM Mode when PNF e 0 (See SLCT and

Table 7-5 for further information)

Write Protect

This input indicates that the disk in the selected drive is write protected

Write Protect

This pin provides an additional Write Protect signal in PPM Mode when PNF e 0 (See PD2

and Table 7-5 for further information)

WRITE

Write Strobe

This signal is used in EPP mode as write strobe It is active low (See STB and Table 7-5 for

further information)

X1OSC

Crystal1Clock

One side of an external 24 MHz crystal is attached here If a crystal is not used a TTL or

CMOS compatible clock is connected to this pin

Crystal2

One side of an external 24 MHz crystal is attached here This pin is left unconnected if an

external clock is used

ZWS

Zero Wait State

This pin is the Zero Wait State open drain output pin when bit 6 of FCR is 0 ZWS is

driven low when the EPP is written and the access can be shortened This pin is either PWDN or CSOUT

when bit 6 of FCR is 1 (See the PWDN and CSOUT pins for further information)

20 Configuration Registers

21 OVERVIEW

Five registers constitute the Base Configuration Register set

which controls the set-up of the PC87322VF In general

these registers control the enabling of each major function

(eg FDC UARTs parallel port pin functionality etc) the

IO addresses of those functions and whether those func-

tions power-down via hardware control or not These five

configuration registers are the Function Enable Register

(FER) the Function Address Register (FAR) the Power and

Test Register (PTR) Function Control Register (FCR) and

Printer Control Register (PCR)

The first three registers can be accessed via hardware or

software During reset the PC87322VF loads a set of de-

fault values selected by a hardware strapping option into the

first three Configuration Registers FCR and PCR can only

be accessed by software

An index and data register pair are used to read and write

these registers Each Configuration Register is pointed to

the value loaded into the Index Register The data to be

written into the Configuration Register is transferred via the

Data register A Configuration Register is read in a similar

way (ie by pointing to it via the Index Register and then

reading its contents via the Data Register)

Accessing the Configuration Registers in this way requires

only two system IO addresses Since that IO space is

shared by other devices the Index and Data Registers could

still be inadvertantly accessed even though there are only

two registers in this IO address space To reduce the

chances of an inadvertent access a simple procedure (Sec-

tion 22) has been developed

22 SOFTWARE CONFIGURATION

If the system requires access to the Configuration Registers

after reset the following procedure is used to change data

in the registers

1 Determine the default location of the PC87322VF Index

A Check the two possible default locations (see Table

2-1) by reading them twice The first byte is the ID byte

(88h) The second byte read is always 00h Compare

the data read with the ID byte and then 00h A match

will occur at the correct location Note that the ID byte

is only issued from the Index Register during the first

read after a reset Subsequent reads return the value

loaded into the Index Register Bits 3 – 6 are reserved

and always read 0

2 Load the Configuration Registers

A Disable CPU interrupts

B Write the index of the Configuration Register (00h –

04h) to the Index Register one time

C Write the correct data for the Configuration Register in

two consecutive write accesses to the Data Register

D Enable CPU interrupts

3 Load the Configuration Registers (read-modify-write)

A Disable CPU interrupts

B Write the index of the Configuration Register (00h –

04h) to the Index Register one time

C Read the configuration data in that register via the

Data Register

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