PC87322VF datasheet(16/84 Pages) NSC

16 / 84 page

20 Configuration Registers (Continued)

Bit 3

When this bit is one the FDC can be accessed at the

address specified in the FER bits When this bit is zero

access to the FDC is blocked and it will be in power-

down mode The FDC registers retain all data in pow-

er-down mode

Bit 4

When this bit is zero the PC87322VF can control two

floppy disk drives directly without an external decoder

When this bit is one the two drive select signals and

two motor enable signals from the FDC are encoded

so that four floppy disk drives can be controlled (see

Table 2-3) Controlling four FDDs requires an external

decoder The pin states shown in Table 2-3 are a di-

rect result of the bit patterns shown All other bit pat-

terns produce pin states that should not be decoded

to enable any drive or motor

Bit 5

This bit selects the primary or secondary FDC ad-

dress

Bit 6

When this bit is a one the IDE drive interface can be

accessed at the address specified by FER bit 7 When

it is zero access to the IDE interface is blocked the

IDE control signals (ie HCS0 HCS1 IDELO IDEHI)

are held in the inactive state and the IDED7 signal will

be in TRI-STATE

Bit 7

This bit selects the primary or secondary IDE address

(See Table 2-4)

TABLE 2-3 Encoded Drive and Motor Pin Information (FER 4 e 1)

Digital Output Register

Drive Control Pins

Decoded Functions

MTR1

MTR0

DR1

DR0

XXX

(Note 1)

Activate Drive 0 and Motor 0

(Note 1)

Activate Drive 1 and Motor 1

(Note 1)

Activate Drive 2 and Motor 2

(Note 1)

Activate Drive 3 and Motor 3

XXX

(Note 1)

Activate Drive 0 and Deactivate Motor 0

(Note 1)

Activate Drive 1 and Deactivate Motor 1

(Note 1)

Activate Drive 2 and Deactivate Motor 2

(Note 1)

Activate Drive 3 and Deactivate Motor 3

Note 1

When FER4 e 1 MTR1 will present a pulse that is the inverted image of the IOW strobe This inverted pulse will be activated whenever an IO write to

address 3F2h or 372h takes place This pulse is delayed by 25 ns–80 ns after the leading edge of IOW and its leading edge can be used to clock data into an

external latch (eg 74LS175) Address 3F2h will be used if the FDC is located at the primary address (FER5 e 0) and address 372h will be used if the FDC is

located at the secondary address (FER5 e 1)

TABLE 2-4 Primary and Secondary Drive Address Selection

BIT 5

BIT 7

DRIVE

Primary

Secondary

FDC

3F0 – 7h

FDC

370 – 7h

FDC

IDE

1F0 – 7 3F6 3F7h

IDE

170 – 7 376 7h

IDE

PC87322VF Datasheet(PDF) 16 Page - National Semiconductor (TI)

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