PC87322VF datasheet(57/84 Pages) NSC

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70 Parallel Port (Continued)

Bit 4

This bit represents the current state of the printer se-

lect signal (SLCT) The printer sets this bit high when it

is selected This bit follows the state of the SLCT pin

Bit 5

This bit represents the current state of the printer pa-

per end signal (PE) The printer sets this bit high when

it detects the end of the paper This bit follows the

state of the PE pin

Bit 6

This bit represents the current state of the printer ac-

knowledge signal (ACK) The printer pulses this signal

low after it has received a character and is ready to

receive another one This bit follows the state of the

ACK pin

Bit 7

This bit (BUSY) represents the current state of the

printer busy signal The printer sets this bit low when it

is busy and cannot accept another character This bit

is the inverse of the (BUSYWAIT) pin

74 CONTROL REGISTER (CTR)

TLC11870 – 21

This register provides all output signals to control the print-

er It is a read and write register except for bit 5

Bit 0

This bit (STB) directly controls the data strobe sig-

nal to the printer via the STB pin This bit is the

inverse of the STB pin

Bit 1

This bit (AFD) directly controls the automatic feed

XT signal to the printer via the AFD pin Setting this

bit high causes the printer to automatically feed

after each line is printed This bit is the inverse of

the AFD pin

Bit 2

This bit (INIT) directly controls the signal to initial-

ize the printer via the INIT pin Setting this bit to

low initializes the printer This bit follows the INIT

Bit 3

This bit (SLIN) directly controls the select in signal

to the printer via the SLIN pin Setting this bit high

selects the printer This bit is the inverse of the

SLIN pin

Bit 4

This bit enables the parallel port interrupt Setting

this bit low puts IRQ57 into TRI-STATE and clears

any pending interrupts

In the AT Compatible

Mode or in EPP mode when bit 4 of PCR is 0

when this bit is set high the appropriate IRQ signal

follows the ACK signal transitions (pulse interrupt)

In the Extended Mode or in EPP mode when bit 4

of PCR is 1 when this bit is set high the appropri-

ate IRQ signal should set high on the 0 to 1 tran-

sition of the ACK signal (level interrupt)

Bit 5

This bit determines the parallel port direction when

bit 7 of PTR is 1 The default condition results in

the parallel port being in the output mode This is a

ReadWrite

bit in EPP mode In SPP mode it is a

write only bit a read from it will return 1 See Table

7-2 for further details

Bits 6 7

Reserved These bits are always 1

TABLE 7-3 Parallel Port Reset States

Signal

Reset Control

State after Reset

SLIN

TRI-STATE

INIT

Zero

AFD

TRI-STATE

STB

TRI-STATE

IRQ5 7

TRI-STATE

Normally when the Control Register is read the bit values

are provided by the internal output data latch These bit

values can be superseded by the logic level of the STB

AFD INIT and SLIN pins if these pins are forced high or

low by an external voltage In order to force these pins high

or low the corresponding bits should be set to their inactive

state (eg AFD e STB e SLIN e 0 INIT e 1)

75 ENHANCED PARALLEL PORT OPERATION

EPP mode provides for greater throughput and more com-

plexity than Compatible or Extended modes by supporting

faster transfer times and a mechanism that allows the host

to address peripheral device registers directly Faster trans-

fers are achieved by automatically generating the address

and data strobes EPP is compatible with both Compatible

and Extended mode parallel-port devices It consists of

eight (0 – 7) single-byte registers (See Table 7-4)

Support for two EPP modes is added to the existing parallel

port

EPP rev 17 is supported when bit 0 of PCR is 1 and bit 1 of

PCR is 0

EPP rev 19 (IEEE 1284) is supported when bit 0 of PCR is

1 and bit 1 of PCR is 1

EPP is supported for a parallel port whose base address is

278h or 378h but not for a parallel port whose base ad-

dress is 3BCh (there are no EPP registers at 3BFh) There

are four EPP transfer operations address write address

read data write and data read An EPP transfer operation is

composed of a host read or write cycle (from or to an EPP

device to an EPP register or from an EPP register to a

peripheral device)

PC87322VF Datasheet(PDF) 57 Page - National Semiconductor (TI)

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