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TMS320F28035MPNTEP Datasheet(PDF) 14 Page - Texas Instruments |
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TMS320F28035MPNTEP Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 144 page ![]() 14 TMS320F28035-EP SPRSP25A – JUNE 2018 – REVISED JULY 2018 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F28035-EP Terminal Configuration and Functions Copyright © 2018, Texas Instruments Incorporated Table 3-1. Signal Descriptions(1) (continued) TERMINAL I/O/Z DESCRIPTION NAME PN PIN NO. GPIO37 58 I/O/Z General-Purpose Input/Output 37 TDO O/Z JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive) GPIO38 57 I/O/Z General-Purpose Input/Output 38 TCK I JTAG test clock with internal pullup XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken to not enable this path for clocking if it is being used for the other functions. – – GPIO39 56 I/O/Z General-Purpose Input/Output 39 – – – – – – GPIO40 64 I/O/Z General-Purpose Input/Output 40 EPWM7A O Enhanced PWM7 output A and HRPWM channel – – – – GPIO41 48 I/O/Z General-Purpose Input/Output 41 EPWM7B O Enhanced PWM7 output B – – – – GPIO42 5 I/O/Z General-Purpose Input/Output 42 – – – – COMP1OUT O Direct output of Comparator 1 GPIO43 6 I/O/Z General-Purpose Input/Output 43 – – – – COMP2OUT O Direct output of Comparator 2 GPIO44 45 I/O/Z General-Purpose Input/Output 44 – – – – – – |
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