TMS320F28035MPNTEP datasheet(39/144 Pages) TI1

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TMS320F28035-EP

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SPRSP25A – JUNE 2018 – REVISED JULY 2018

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Detailed Description

5.1.12 External Interrupts (XINT1–XINT3)

The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be

selected for negative, positive, or both negative and positive edge triggering and can also be

enabled/disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero

when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt.

There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept

inputs from GPIO0–GPIO31 pins.

5.1.13 Internal Zero Pin Oscillators, Oscillator, and PLL

The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a

crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 12 input-clock-scaling

ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating

frequency if lower power operation is desired. Refer to Section 4, Electrical Specifications, for timing

details. The PLL block can be set in bypass mode.

5.1.14 Watchdog

Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a

missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a

certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog

can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either

generate an interrupt or a device reset.

5.1.15 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a

peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled

relative to the CPU clock.

5.1.16 Low-power Modes

The devices are full static CMOS devices. Three low-power modes are provided:

IDLE:

Place CPU in low-power mode. Peripheral clocks may be turned off selectively and

only those peripherals that must function during IDLE are left operating. An enabled

interrupt from an active peripheral or the watchdog timer will wake the processor from

IDLE mode.

STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL

functional. An external interrupt event will wake the processor and the peripherals.

Execution begins on the next valid cycle after detection of the interrupt event

HALT:

This mode basically shuts down the device and places it in the lowest possible power

consumption mode. If the internal zero-pin oscillators are used as the clock source,

the HALT mode turns them off, by default. To keep these oscillators from shutting

down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin

oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip

crystal oscillator is used as the clock source, it is shut down in this mode. A reset or

an external signal (through a GPIO pin) or the CPU-watchdog can wake the device

from this mode.

The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put

the device into HALT or STANDBY.

TMS320F28035MPNTEP Datasheet(PDF) 39 Page - Texas Instruments

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