TMS320F28035MPNTEP datasheet(29/144 Pages) TI1

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TMS320F28035-EP

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SPRSP25A – JUNE 2018 – REVISED JULY 2018

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Specifications

4.13 Clock Specifications

4.13.1 Device Clock Table

This section provides the timing requirements and switching characteristics for the various clock options

available on the 2803x MCUs. Table 4-6 lists the cycle times of various clocks.

(1)

Lower LSPCLK will reduce device power consumption.

(2)

This is the default reset value if SYSCLKOUT = 60 MHz.

Table 4-6. 2803x Clock Table and Nomenclature (60-MHz Devices)

MIN

NOM

MAX

UNIT

SYSCLKOUT

tc(SCO), Cycle time

16.67

500

Frequency

MHz

LSPCLK(1)

tc(LCO), Cycle time

16.67

66.67(2)

Frequency

15(2)

MHz

ADC clock

tc(ADCCLK), Cycle time

16.67

Frequency

MHz

(1)

The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are

used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).

Table 4-7. Device Clocking Requirements/Characteristics

MIN

NOM

MAX

UNIT

On-chip oscillator (X1/X2 pins)

(Crystal/Resonator)

tc(OSC), Cycle time

200

Frequency

MHz

External oscillator/clock source

(XCLKIN pin) — PLL Enabled

tc(CI), Cycle time (C8)

33.3

200

Frequency

MHz

External oscillator/clock source

(XCLKIN pin) — PLL Disabled

tc(CI), Cycle time (C8)

33.33

250

Frequency

MHz

Limp mode SYSCLKOUT

(with /2 enabled)

Frequency range

1 to 5

MHz

XCLKOUT

tc(XCO), Cycle time (C1)

66.67

2000

Frequency

0.5

MHz

PLL lock time(1)

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