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TMS320F28035MPNTEP Datasheet(PDF) 59 Page - Texas Instruments |
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TMS320F28035MPNTEP Datasheet(HTML) 59 Page - Texas Instruments |
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59 / 144 page ![]() /512 WDCLK WDCR (WDPS[2:0]) WDCLK WDCNTR(7:0) WDKEY(7:0) Good K ey 1 0 1 WDCR (WDCHK[2:0]) Bad WDCHK Key WDCR (WDDIS) Clear Counter SCSR (WDENINT) Watchdog Prescaler Generate Output Pulse (512 OSCCLKs) 8-Bit Watchdog Counter CLR WDRST WDINT Watchdog 55 + AA Key Detector Core-reset XRS WDRST(A) Internal Pullup 59 TMS320F28035-EP www.ti.com SPRSP25A – JUNE 2018 – REVISED JULY 2018 Submit Documentation Feedback Product Folder Links: TMS320F28035-EP Detailed Description Copyright © 2018, Texas Instruments Incorporated A. The WDRST signal is driven low for 512 OSCCLK cycles. Figure 5-8. CPU-watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 5.7, Low-power Modes Block, for more details. In IDLE mode, the WDINT signal can generate an interrupt to the CPU, through the PIE, to take the CPU out of IDLE mode. In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset. |
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