TMS320F28035MPNTEP datasheet(34/144 Pages) TI1

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TMS320F28035-EP

SPRSP25A – JUNE 2018 – REVISED JULY 2018

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Detailed Description

5.1

Overview

5.1.1

CPU

The 28035 (C28x) is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28x-based

controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very efficient

C/C++ engine, enabling users to develop not only their system control software in a high-level language,

but also enabling development of math algorithms using C/C++. The device is as efficient at MCU math

tasks as it is at system control tasks that typically are handled by microcontroller devices. This efficiency

removes the need for a second processor in many systems. The 32 × 32-bit MAC 64-bit processing

capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this the

fast interrupt response with automatic context save of critical registers, resulting in a device that is capable

of servicing many asynchronous events with minimal latency. The device has an 8-level-deep protected

pipeline with pipelined memory accesses. This pipelining enables it to execute at high speeds without

resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency

for conditional discontinuities. Special store conditional operations further improve performance.

5.1.2

Control Law Accelerator (CLA)

The C28x control law accelerator is a single-precision (32-bit) floating-point unit that extends the

capabilities of the C28x CPU by adding parallel processing. The CLA is an independent processor with its

own bus structure, fetch mechanism, and pipeline. Eight individual CLA tasks, or routines, can be

specified. Each task is started by software or a peripheral such as the ADC, an ePWM, or CPU Timer 0.

The CLA executes one task at a time to completion. When a task completes the main CPU is notified by

an interrupt to the PIE and the CLA automatically begins the next highest-priority pending task. The CLA

can directly access the ADC Result registers and the ePWM+HRPWM registers. Dedicated message

RAMs provide a method to pass additional data between the main CPU and the CLA.

5.1.3

Memory Bus (Harvard Bus Architecture)

As with many MCU-type devices, multiple buses are used to move data between the memories and

peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and

data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and

write buses consist of 32 address lines and 32 data lines each. The 32-bit-wide data buses enable single

cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x

to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and

memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus

accesses can be summarized as follows:

Highest:

Data Writes

(Simultaneous data and program writes cannot occur on the

memory bus.)

Program Writes

(Simultaneous data and program writes cannot occur on the

memory bus.)

Data Reads

Program Reads

(Simultaneous program reads and fetches cannot occur on the

memory bus.)

Lowest:

Fetches

(Simultaneous program reads and fetches cannot occur on the

memory bus.)

TMS320F28035MPNTEP Datasheet(PDF) 34 Page - Texas Instruments

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