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SW4STM32C Datasheet(PDF) 52 Page - STMicroelectronics |
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SW4STM32C Datasheet(HTML) 52 Page - STMicroelectronics |
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52 / 99 page  Exception handling AN4989 52/99 DocID030181 Rev 2 6.3.2 Cortex®-M3/4/7 case For targets that support hardware division instructions, Trapping of DIV0 operation is possible by configuring System Control Block (SCB) registers, accessible through CMSIS library. For example on Cortex®-M3: SCB_CCR register description is provided in Figure 33. Figure 33. Cortex®-M3 SCB_CCR Description Refer to STM32F10xxx/20xxx/21xxx/L1xxxx Cortex-M3 programming manual (PM0056). Setting bit 5 of SCB_CCR register SCB->CCR |= 0x10; // enable div-by-0 trap When Div0 occurs it is trapped in HardFault_Handler. With breakpoint on while instruction into HardFault_Handler, CallStack point to the offended line and SCB->CFSR register explicits the type of fault SCB_CFSR register description is provided in Figure 34. Figure 34. Cortex-M3 SCB_CFSR Description The following sections describe the management of SCB registers as a function of the selected IDE. |
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