LPC5410X datasheet(34/95 Pages) NXP

34 / 95 page

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

34 of 95

NXP Semiconductors

LPC5410x

32-bit ARM Cortex-M4/M0+ microcontroller

7.20.3 Clock Generation

7.20.4 Power control

The LPC5410x support a variety of power control features. In Active mode, when the chip

is running, power and clocks to selected peripherals can be optimized for power

consumption. In addition, there are four special modes of processor power reduction with

different peripherals running: Sleep mode, deep sleep mode, power down mode, and

deep power-down mode, activated by the power mode configure API.

Fig 7.

LPC5410x clock generation

System PLL

settings

sysclk

pll_clk

System clock divider

AHBCLKDIV[7:0]

Main clock select B

MAINCLKSELB[1:0]

32k_clk

CPU Clock

Divider

System PLL

(PLL0)

CLKIN

Main clock select A

MAINCLKSELA[1:0]

wdt_clk

irc_clk

PLL clock select

SYSPLLCLKSEL[1:0]

main clock

CLKIN

pll_clk

APB clock select B

ASYNCAPBCLKSELB[1:0]

wdt_clk

irc_clk

pll_clk

irc_clk

ADC clock select

ADCCLKSEL[1:0]

APB clock select A

ASYNCAPBCLKSELA[1:0]

CLKIN

irc_osc

CLKOUT select A

CLKOUTSELA[1:0]

wdt_clk

32k_osc

CLKOUT select B

CLKOUTSELB[1:0]

CLKOUTDIV[7:0]

CLKOUT

AD C clock divider

ADCCLKDIV[7:0]

ADC Clock

Divider

Async APB clock divider

ASYNCAPBCLKDIV[7:0]

Async APB

Divider

to async

APB bridge

to ADC

to CPU, AHB

bus, Sync

APB, etc.

CLKOUT

Divider

main clock

aaa-015553

CLKIN

32k_clk

irc_clk

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