LPC5410X datasheet(70/95 Pages) NXP

70 / 95 page

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

70 of 95

NXP Semiconductors

LPC5410x

32-bit ARM Cortex-M4/M0+ microcontroller

12.2 12-bit ADC characteristics

[1]

Based on characterization; not tested in production.

[2]

Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply

voltages.

[3]

The input resistance of ADC channels 6 to 11 is higher than ADC channels 0 to 5.

[4]

Cia represents the external capacitance on the analog input channel for sampling speeds of

5.0 Msamples/s. No parasitic capacitances included.

[5]

The differential linearity error (ED) is the difference between the actual step width and the ideal step width.

See Figure 24.

[6]

The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 24.

[7]

The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the

straight line which fits the ideal curve. See Figure 24.

[8]

The full-scale error voltage or gain error (EG) is the difference between the straight-line fitting the actual

transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See

Figure 24.

[9]

Tamb = 25 C; maximum sampling frequency fs = 5.0 Msamples/s and analog input capacitance Cia = 5 pF.

[10] Input impedance Zi is inversely proportional to the sampling frequency and the total input capacity including

Cia and Cio: Zi  1 / (fs  Ci). See Table 16 for Cio. See Figure 25.

Table 31.

12-bit ADC static characteristics

Tamb = 40 C to +105 C; 1.62 V  VDD  3.6 V; VREFP = VDDA; VSSA = VREFN = GND. ADC

calibrated at Tamb = 25C.

Symbol Parameter

Conditions

Min

Typ[2] Max

Unit

VIA

analog input

voltage

[3] 0-

VDDA

Cia

analog input

capacitance

[4] -5

fclk(ADC) ADC clock

frequency

MHz

sampling

frequency

5.0

Msamples/s

differential

linearity error

VDDA = VREFP = 1.62 V [1][5] -

3

LSB

VDDA = VREFP = 3.6 V

2

LSB

EL(adj)

integral

non-linearity

VDDA = VREFP = 1.62 V [1][6] -

5

LSB

VDDA = VREFP = 3.6 V

2

LSB

offset error

calibration enabled

[1][7] -

5.6

Verr(FS)

full-scale error

voltage

VDDA = VREFP = 1.62 V [1][8] -

3

LSB

VDDA = VREFP = 3.6 V

3

LSB

input

impedance

fs = 5.0 Msamples/s

[9][10] 17.0



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