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LPC5410X Datasheet(PDF) 42 Page - NXP Semiconductors |
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LPC5410X Datasheet(HTML) 42 Page - NXP Semiconductors |
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42 / 95 page ![]() LPC5410x All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 2.11 — 19 September 2019 42 of 95 NXP Semiconductors LPC5410x 32-bit ARM Cortex-M4/M0+ microcontroller [2] Clock source 12 MHz IRC. PLL enabled. [3] Characterized through bench measurements using typical samples. [4] Compiler settings: Keil μVision v.5.12, optimization level 3, optimized for time on. [5] SRAM0 and SRAM1 powered, SRAM2 powered down. [6] See the FLASHCFG register in the LPC5410x User Manual for system clock flash access time settings. Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals except one UART; BOD disabled; SRAM0 and SRAM1 powered, SRAM2 powered down. See the FLASHCFG register in the LPC5410x User Manual for system clock flash access time settings. Measured with Keil uVision 5.12. Optimization level 3, optimized for time on. 12 MHz: IRC enabled; PLL disabled. 24 MHz - 100 MHz: IRC enabled; PLL enabled. Fig 8. Typical CoreMark score aaa-015950 12 24 36 48 60 72 84 96 108 1 1.4 1.8 2.2 2.6 3 Frequency (MHz) Coremark score Coremark score Coremark score (iterations/s) / MHz) (iterations/s) / MHz) (iterations/s) / MHz) M4 SRAM M4 SRAM M4 SRAM M4 Flash M4 Flash M4 Flash |
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