LPC5410X datasheet(67/95 Pages) NXP

67 / 95 page

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

67 of 95

NXP Semiconductors

LPC5410x

32-bit ARM Cortex-M4/M0+ microcontroller

11.11 USART interface

The actual USART bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for USART

master and slave synchronous modes is 24 Mbit/s.

Table 28.

USART dynamic characteristics[1]

Tamb = 40 C to 105 C; 1.62 V  VDD  3.6 V; CL = 30 pF balanced loading on all pins; SLEW =

standard mode. Parameters sampled at the 50% level of the falling or rising edge.

Symbol Parameter

Conditions

Min

Max

Unit

USART master (in synchronous mode) 1.62V

 VDD  2.0 V

tsu(D)

data input set-up time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

th(D)

data input hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

tv(Q)

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

USART slave (in synchronous mode) 1.62V

 VDD  2.0 V

tsu(D)

data input set-up time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

th(D)

data input hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

tv(Q)

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

USART master (in synchronous mode) 2.7V

 VDD  3.6V

tsu(D)

data input set-up time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

th(D)

data input hold time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

tv(Q)

data output valid time

CCLK = 1 MHz to 12 MHz

CCLK = 48 MHz to 60 MHz

CCLK = 96 MHz

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