LPC5410X datasheet(45/95 Pages) NXP

45 / 95 page

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

45 of 95

NXP Semiconductors

LPC5410x

32-bit ARM Cortex-M4/M0+ microcontroller

[1]

Typical ratings are not guaranteed. Typical values listed are at room temperature (25

C), 3.3V.

[2]

Clock source 12 MHz IRC. PLL disabled.

[3]

Clock source 12 MHz IRC. PLL enabled.

[4]

Characterized through bench measurements using typical samples.

[5]

Compiler settings: Keil μVision v.5.10, optimization level 0, optimized for time off.

[6]

Prefetch disabled in FLASHCFG register. System clock flash access time set by power API. SRAM0 powered, SRAM1 and SRAM2

powered down.Compiler settings: Keil μVision v.5.12, optimization level 0, optimized for time off.

[7]

First 8 kB in SRAM0 powered; Flash, SRAM1, and SRAM2 are powered down; all peripheral clocks disabled. Compiler settings: Keil

μVision v.5.12, optimization level 0, optimized for time off.

ARM Cortex-M4 in sleep mode; ARM Cortex-M0+ in sleep mode

IDD

supply current

CCLK = 12 MHz

[2][4][7]

990

A

CCLK = 100 MHz

[3][4][7]

4.0

Table 11.

Static characteristics: Power consumption in active and sleep modes

Tamb = 40 C to +105 C, unless otherwise specified.1.62 V  VDD  3.6 V.

Symbol

Parameter

Conditions

Min

Typ[1]

Max

Unit

Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals disabled; BOD disabled;

Prefetch disabled in FLASHCFG register. System clock flash access time set by power API.

SRAM0 powered, SRAM1 and SRAM2 powered down. Measured with Keil uVision 5.12.

Optimization level 0, optimized for time off.

12 MHz: IRC enabled; PLL disabled. 24 MHz - 100 MHz: IRC enabled; PLL enabled.

Fig 9.

CoreMark power consumption: typical

A/MHz for M4 and M0+ cores

aaa-015966

108

110

140

170

Frequency (MHz)

μ/MHz

M4F SRAM

M0+ SRAM

M4F Flash

M0+ Flash

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