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W5200 Datasheet(PDF) 81 Page - WIZnet Co., Ltd |
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W5200 Datasheet(HTML) 81 Page - WIZnet Co., Ltd |
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81 / 88 page  © Copyright 2013 WIZnet Co.,Ltd. All rights reserved. 81 7.4.3 SPI Timing Figure 24 SPI Timing 5 Theoretical Guaranteed Speed Even though theoretical design speed is 80MHz, the signal in the high speed may be distorted because of the circuit crosstalk and the length of the signal line. The minimum guaranteed speed of the SCLK is 33.3 MHz which was tested and measured with the stable waveform. 6 2.1ns is when pn loaded with 30pF. The time is shorter with lower capacitance. Symbol Description Min Max Units FSCK SCK Clock Frequency 80/33.35 MHz TWH SCK High Time 6 ns TWL SCK Low Time 6 ns TCS CSn High Time 5 ns TCSS CSn Setup Time 5 - ns TCSH CSn Hold Time 5 ns TDS Data In Setup Time 3 ns TDH Data In Hold Time 3 ns TOV Output Valid Time 5 ns TOH Output Hold Time 0 ns TCHZ CSn High to Output Hi-Z 2.16 ns |
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