AD9083BBCZ datasheet(74/93 Pages) AD

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AD9083

Data Sheet

Rev. 0 | Page 74 of 93

Addr.

Name

Bits

Bit Name

Description

Reset Access

0x1C0 SYNC_CTRL1

[7:4]

RESERVED

Reserved.

0x1

NCORESET_ALL_SYSREF

NCO Reset Control by SYSREF. Applicable only in

resynchronization mode.

0: NCO reset happens only with a SYSREF which

caused resynchronization of clocks.

1: NCO reset happens with all SYSREF pulses (not

recommended unless SYSREF period is much

greater LMFC periods).

0x1

R/W

SYSREF_RESYNC_MODE

SYSREF Resync Mode.

0: SYSREF is not used for resync

1: SYSREF is used for resync

0x0

R/W

RISEDGE_SYSREF

Risedge SYSREF.

0: No rise edge detection on SYSREF pin. Input

SYSREF used as such

1: Rise edge detection done on input SYSREF and

used.

0x0

R/W

DP_CLK_FORCEN

Reserved.

0x0

R/W

0x1C1 TRIG_PROG_DELAY

[7:0]

TRIG_PROG_DELAY

Programmable delay for input trig in terms of

fS/4 clock cycles.

0x0

R/W

0x1C2 SYSREF_PROG_DELAY

[7:0]

SYSREF_PROG_DELAY

Programmable delay for input SYSREF terms of

fS/2 clock cycles.

0x0

R/W

0x1C3 TRIG_CTRL

[7:6]

TRIG_EDGE_CTRL

Control for Trig Edge Detection.

0x0

R/W

00: No Edge Detection.

01: Positive Edge.

10: Negative Edge.

[5:0]

RESERVED

Reserved.

0x10

R/W

0x1C4 DDC_SYNC_CTRL

[7:5]

RESERVED

Reserved.

0x0

R/W

DDC_SOFT_RESET

Digital Down Converter Soft Reset. Digital Down

Converter Soft Reset

0: Normal Operation

1: DDC Held in Reset.

Note: this bit can be used to synchronize all the

NCOs inside the DDC blocks.

0x0

R/W

[3:2]

RESERVED

Reserved.

0x0

DDC_SYNC_NEXT

DDC Next Synchronization Mode. DDC Next

Synchronization Mode

0: Continuous mode

1: Next Synchronization mode - only the next

valid edge of SYSREF pin will be used to

synchronize the NCO in the DDC block.

Subsequent edges of the SYSREF pin will be

ignored.

Note: The SYSREF pin must an integer multiple of

the NCO frequency in order for this function to

operate correctly in continuous mode.

0x1

R/W

DDC_SYNC_EN

DDC Synchronization Enable. DDC

Synchronization Enable

0: Synchronization Disabled

1: Synchronization Enabled. If DDC_SYNC_

NEXT = 1, only the next valid edge of the SYSREF

pin will be used to synchronize the NCO in the

DDC block. Subsequent edges of the SYSREF pin

are ignored. After the next SYSREF is received,

this must be cleared for any subsequent use of

next SYSREF.

Note: the SYSREF input pin must be enabled in

order to synchronize the DDCs.

0x0

R/W

AD9083BBCZ Datasheet(PDF) 74 Page - Analog Devices

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