TMS320F28375DPZP datasheet(143/226 Pages) TI

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8.11.5.2 SDFM Electrical Data and Timing (Using 3-Sample GPIO Input Qualification)

SDFM operation with qualified GPIO (3-sample window) is defined by setting GPyQSELn = 0b01. When using

this qualified GPIO (3-sample window) mode, the timing requirement for the tw(GPI) pulse duration of 2tc(SYSCLK)

must be met. It is important for both SD-Cx and SD-Dx pairs to be configured with the same GPIO qualification

option. Section 8.11.5.2.1 lists the SDFM timing requirements when using the GPIO input qualification (3-sample

window) option. Figure 8-56 through Figure 8-59 show the SDFM timing diagrams.

8.11.5.2.1 SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window) Option

MIN(1)

MAX

UNIT

Mode 0

tc(SDC)M0

Cycle time, SDx_Cy

10 * SYSCLK period

256 * SYSCLK period

tw(SDCHL)M0

Pulse duration, SDx_Cy high/low

4 * SYSCLK period

6 * SYSCLK period

tw(SDDHL)M0

Pulse duration, SDx_Dy high/low

4 * SYSCLK period

tsu(SDDV-SDCH)M0

Setup time, SDx_Dy valid before SDx_Cy goes

high

2 * SYSCLK period

th(SDCH-SDD)M0

Hold time, SDx_Dy wait after SDx_Cy goes high

2 * SYSCLK period

Mode 1

tc(SDC)M1

Cycle time, SDx_Cy

20 * SYSCLK period

256 * SYSCLK period

tw(SDCH)M1

Pulse duration, SDx_Cy high

4 * SYSCLK period

6 * SYSCLK period

tw(SDDHL)M1

Pulse duration, SDx_Dy high/low

4 * SYSCLK period

tsu(SDDV-SDCL)M1

Setup time, SDx_Dy valid before SDx_Cy goes

low

2 * SYSCLK period

tsu(SDDV-SDCH)M1

Setup time, SDx_Dy valid before SDx_Cy goes

high

2 * SYSCLK period

th(SDCL-SDD)M1

Hold time, SDx_Dy wait after SDx_Cy goes low

2 * SYSCLK period

th(SDCH-SDD)M1

Hold time, SDx_Dy wait after SDx_Cy goes high

2 * SYSCLK period

Mode 2

tc(SDD)M2

Cycle time, SDx_Dy

Option unavailable

tw(SDDH)M2

Pulse duration, SDx_Dy high

Mode 3

tc(SDC)M3

Cycle time, SDx_Cy

10 * SYSCLK period

256 * SYSCLK period

tw(SDCHL)M3

Pulse duration, SDx_Cy high

4 * SYSCLK period

6 * SYSCLK period

tw(SDDHL)M3

Pulse duration, SDx_Dy high/low

4 * SYSCLK period

tsu(SDDV-SDCH)M3

Setup time, SDx_Dy valid before SDx_Cy goes

high

2 * SYSCLK period

th(SDCH-SDD)M3

Hold time, SDx_Dy wait after SDx_Cy goes high

2 * SYSCLK period

(1)

SDFM timing requirements apply only when the GPIO input qualification type is the 3-sample window (GPyQSELx = 1; QUALPRD = 0)

option. It is important that both the SD-Cx and SD-Dx pairs be configured with the 3-sample window option.

Note

The SDFM Qualified GPIO (3-sample) mode provides protection against SDFM module corruption due

to occasional random noise glitches on the SDx_Cy pin that may result in a false comparator trip and

filter output. For more details, refer to the "SDFM: Use Caution While Using SDFM Under Noisy

Conditions" usage note in the TMS320F2837xD Dual-Core MCUs Silicon Errata .

The SDFM Qualified GPIO (3-sample) mode does not provide protection against persistent violations

of the above timing requirements. Timing violations will result in data corruption proportional to the

number of bits which violate the requirements.

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TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

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SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

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