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MCP39F511N Datasheet(PDF) 36 Page - Microchip Technology |
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MCP39F511N Datasheet(HTML) 36 Page - Microchip Technology |
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36 / 61 page ![]() 2015-2018 Microchip Technology Inc. DS20005473B-page 36 MCP39F511N REGISTER 6-4: RANGE2 REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 31 bit 24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POWER2[7] POWER2[6] POWER2[5] POWER2[4] POWER2[3] POWER2[2] POWER2[1] POWER2[0] bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CUR- RENT2[7] CUR- RENT2[6] CUR- RENT2[5] CUR- RENT2[4] CUR- RENT2[3] CUR- RENT2[2] CUR- RENT2[1] CUR- RENT2[0] bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0‘ bit 23-16 POWER2[7:0]: Sets the number of right-bit shifts for the Active and Reactive Power output registers, channel 2 bit 15-8 CURRENT2[7:0]: Sets the number of right-bit shifts for the Current RMS output register, channel 2. bit 7-0 Unimplemented: Read as ‘0‘ |
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