MCP39F511N datasheet(12/61 Pages) MICROCHIP

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 2015-2018 Microchip Technology Inc.

DS20005473B-page 12

MCP39F511N

3.1

Event Output Pins (EVENTn)

These digital output pins can be configured to act as

output flags based on various internal raise conditions.

Control is modified through the Event Configuration

3.2

UART Communication Pins

(UART_RX, UART_TX)

The MCP39F511N device contains an asynchronous

full-duplex UART. The UART communication is eight

bits with the Start and Stop bits. See Section 4.3

“UART Settings” for more information.

3.3

Common Pins (COMMON A and B)

The COMMONA and COMMONB pins are internal

connections for the MCP39F511N. These two pins

should be connected together in the application.

3.4

Oscillator Pins (OSCI/OSCO)

OSCI and OSCO provide the master clock for the

device. Appropriate load capacitance should be

connected to these pins for proper operation. An

optional 8 MHz crystal can be connected to these pins.

If a crystal or external clock source is not detected, the

device will clock from the internal 8 MHz oscillator.

3.5

Reset Pin (RESET)

This pin is active-low and places the Delta-Sigma

ADCs, PGA, internal VREF and other blocks associated

with the analog front-end in a Reset state when pulled

low. This input is Schmitt-triggered.

3.6

Master Clear Pin (MCLR)

This pin places the SAR, ADC, Calculation Engine,

UART serial interface and digital outputs in a Reset

state when pulled low. This input is Schmitt-triggered.

3.7

Analog Power Supply Pin (AVDD)

AVDD is the power supply pin for the analog circuitry

within the MCP39F511N.

This pin requires appropriate bypass capacitors and

should be maintained to 2.7V and 3.6V for specified

operation. It is recommended to use 0.1 µF ceramic

capacitors.

3.8

Pulse-Width Modulator (PWM)

This digital output is a dedicated PWM output that can

be controlled through the PWM Frequency and PWM

Duty-Cycle Registers. See Section 8.0 “Pulse-Width

modulation (PWM)” for more information.

3.9

24-Bit Delta-Sigma ADC

Differential Current Channel

Input Pins (I1+/I1-/I2+/I2-)

(I1-, I1+), (I2-, I2+) are the two fully-differential

current-channel pair inputs for the Delta-Sigma ADCs.

The linear and specified region of the channels are

dependent on the PGA gain. This region corresponds

to a differential voltage range of ±600 mVPEAK/GAIN

with VREF =1.2V.

The maximum absolute voltage, with respect to AGND,

for each In+/- input pin is ±1V with no distortion and

±2V with no breaking after continuous voltage.

3.10

Voltage Analog Input (V+)

This is the non-inverting input to the SAR ADC for

voltage measurement input. This input is used as the

voltage measurement for both channel 1 and channel

2. A DC offset of DVDD/2 and no more than 1 VRMS AC

input signal should be applied on the pin as shown in

the typical application schematic.

3.11

Analog Ground Pin (AGND)

AGND is the ground connection to internal analog

circuitry (ADCs, PGA, voltage reference, POR). If an

analog ground pin is available on the PCB, it is

recommended that this pin be tied to that plane.

3.12

Zero Crossing Detection (ZCD)

This digital output pin is the output of the zero crossing

detection circuit of the IC. The output here will be a

logic output with edges that transition at each zero

crossing of the voltage channel input. For more

information

see

Section 5.10

“Zero

Crossing

Detection (ZCD)”.

3.13

Non-Inverting Reference

Input/Internal Reference Output

Pin (REFIN+/OUT)

This pin is the non-inverting side of the differential

voltage reference input for the Delta-Sigma ADCs or

the internal voltage reference output.

For optimal performance, bypass capacitances should

be connected between this pin and AGND at all times,

even when the internal voltage reference is used.

However, these capacitors are not mandatory to

ensure proper operation.

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