PIMXRT516SCVJ2A datasheet(15/128 Pages) NXP

15 / 128 page

Modules list

i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021

NXP Semiconductors

JTAGC

JTAG Controller

System Control

Peripherals

The JTAG interface complies with JTAG TAP standards

to internal logic. The i.MX RT1170 processors use JTAG

port for production, testing, and system debugging. In

addition, the JTAG provides BSR (Boundary Scan

1149.1 and IEEE 1149.6 standards.

The JTAG port must be accessible during platform initial

laboratory bring-up, for manufacturing tests and

troubleshooting, as well as for software debugging by

authorized entities. The i.MX RT1170 JTAG

incorporates two security modes for protecting against

unauthorized accesses. Modes are selected through

eFUSE configuration.

KPP

Keypad Port

Human Machine

Interfaces

The KPP is a 16-bit peripheral that can be used as a

keypad matrix interface or as general purpose

input/output (I/O). It supports 8 x 8 external key pad

matrix. Main features are:

• Multiple-key detection

• Long key-press detection

• Standby key-press detection

• Supports a 2-point and 3-point contact key matrix

LCDIFv2

Parallel RGB LCD

interface version 2

Multimedia

Peripherals

The LCDIFv2 is an enhanced version of LCDIF.

Main features are:

• Eight layers of alpha blending

• CRC check for configurable region on the final

display output after alpha blending

• Write-back channel to save the final output into

memory

LPI2C1

LPI2C2

LPI2C3

LPI2C4

LPI2C5

LPI2C6

Low Power

Inter-integrated Circuit

Connectivity and

Communications

The LPI2C is a low power Inter-Integrated Circuit (I2C)

module that supports an efficient interface to an I2C bus

as a master.

The I2C provides a method of communication between

a number of external devices. More detailed information,

see Section 4.9.2, LPI2C module timing parameters.

LPSPI1

LPSPI2

LPSPI3

LPSPI4

LPSPI5

LPSPI6

Low Power Serial

Peripheral Interface

Connectivity and

Communications

The LPSPI is a low power Serial Peripheral Interface

(SPI) module that support an efficient interface to an SPI

bus as a master and/or a slave.

• It can continue operating while the chip is in stop

modes, if an appropriate clock is available

• Designed for low CPU overhead, with DMA off

loading of FIFO register access

Table 3. i.MX RT1170 modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

PIMXRT516SCVJ2A Datasheet(PDF) 15 Page - NXP Semiconductors

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