PIMXRT516SCVJ2A datasheet(34/128 Pages) NXP

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i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021

NXP Semiconductors

Electrical characteristics

Set Point #5

Active

• CM7 runs at 240 MHz, lower voltage to 0.9 V

• CM7 domain bus frequency at 100 MHz

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• 16 MHz, 400 MHz, external 24 MHz crystal, and

external 32 kHz crystal are enabled

• All PLLs are enabled

• All peripherals are enabled and run at their

maximum clock root frequency under underdrive

mode

DCDC_IN

38.6

54.3

VDD_LPSR_IN

28.2

30.6

A

VDD_SNVS_IN

3.7

7.3

A

Total

127.485

179.315

Set Point #7

Active

• CM7 runs at 200 MHz, lower voltage to 0.9 V

• CM7 domain bus frequency at 100 MHz

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• 16 MHz, 400 MHz, and external 32 kHz crystal are

enabled

• All PLLs are power gated

• All peripherals are clocked

DCDC_IN

19.4

34.1

VDD_LPSR_IN

28.1

30.4

A

VDD_SNVS_IN

3.7

7.2

A

Total

64.125

112.654

Set Point #1

Standby

Suspend

• System is on STANDBY mode

• CM7 is on SUSPEND mode

• TCM is on retention

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• All clock sources are turned off except for 32 kHz

RTC

• All PLLs are power gated

• All peripherals are clock gated, but remain

powered

DCDC_IN

2.4

VDD_LPSR_IN

22.6

38.2

A

VDD_SNVS_IN

3.7

7.2

A

Total

8.007

29.850

Set Point #0

Standby

Suspend

• System is on STANDBY mode

• CM7 is on SUSPEND mode

• TCM is on retention

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• All clock sources are turned off except for 32 kHz

RTC

• All PLLs are power gated

• All peripherals are clock gated, but remain

powered

DCDC_IN

1.8

VDD_LPSR_IN

22.5

38.3

A

VDD_SNVS_IN

3.7

7.3

A

Total

6.026

23.250

Set Point #5

Standby

Suspend

• System is on STANDBY mode

• CM7 is on SUSPEND mode

• TCM is on retention

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• All clock sources are turned off except for 32 kHz

RTC

• All PLLs are power gated

• All peripherals are clock gated, but remain

powered

DCDC_IN

1.4

5.5

VDD_LPSR_IN

22.3

38.2

A

VDD_SNVS_IN

3.7

7.3

A

Total

4.706

18.300

Table 14. Typical power modes current and power consumption (Single core) (continued)

PIMXRT516SCVJ2A Datasheet(PDF) 34 Page - NXP Semiconductors

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