PIMXRT516SCVJ2A datasheet(32/128 Pages) NXP

32 / 128 page

i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021

NXP Semiconductors

Electrical characteristics

Set Point #0

Standby

Suspend

• System is on STANDBY mode

• Both CM7 and CM4 are on SUSPEND mode

• TCM is on retention

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• All clock sources are turned off except for 32 kHz

RTC

• All PLLs are power gated

• All peripherals clock gated, but remain powered

DCDC_IN

1.8

VDD_LPSR_IN

22.2

38.6

A

VDD_SNVS_IN

3.7

7.6

A

Total

6.025

23.252

Set Point #5

Standby

Suspend

• System is on STANDBY mode

• Both CM7 and CM4 are on SUSPEND mode

• TCM is on retention

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• All clock sources are turned off except for 32 kHz

RTC

• All PLLs are power gated

• All peripherals are clock gated, but remain

powered

DCDC_IN

1.4

5.5

VDD_LPSR_IN

22.2

38.6

A

VDD_SNVS_IN

3.7

7.6

A

Total

4.705

18.302

Set Point #7

Standby

Suspend

• System is on STANDBY mode

• Both CM7 and CM4 are on SUSPEND mode

• TCM is on retention

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• All clock sources are turned off except for 32 kHz

RTC

• All PLLs are power gated

• All peripherals are clock gated, but remain

powered

DCDC_IN

1.4

5.5

VDD_LPSR_IN

22.1

38.6

A

VDD_SNVS_IN

3.7

7.6

A

Total

4.705

18.302

Set Point #10

Standby

Suspend

• Lower voltage to 0.8 V with RBB mode for both

SOC and LPSR domains

• System is on STANDBY mode

• Both CM7 and CM4 are on SUSPEND mode

• TCM is on retention

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• All clock sources are turned off except for 32 kHz

RTC

• All PLLs are power gated

• All peripherals are clock gated, but remain

powered

DCDC_IN

1.2

4.4

VDD_LPSR_IN

22.3

38.7

A

VDD_SNVS_IN

3.7

7.6

A

Total

4.046

14.673

Set Point #11

Standby

Suspend

• System is on STANDBY mode

• CM7 is power off, CM4 is on SUSPEND mode

• CM4 TCM is on retention

• DCDC is off, LDO_LPSR_ANA and

LDO_LPSR_DIG are active

• All clock sources are turned off except for 32 kHz

RTC

• All PLLs are power gated

• The WAKEUPMIX domain, MEGAMIX domain,

and DISPLAYMIX domain are power gated

• All peripherals in LPSRMIX domain are clock

gated, but remain powered

DCDC_IN

24.2

32.7

A

VDD_LPSR_IN

0.364

2.2

VDD_SNVS_IN

3.7

7.5

A

Total

1.293

7.393

Table 13. Typical power modes current and power consumption (Dual core) (continued)

PIMXRT516SCVJ2A Datasheet(PDF) 32 Page - NXP Semiconductors

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