PIMXRT516SCVJ2A datasheet(16/128 Pages) NXP

16 / 128 page

i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021

NXP Semiconductors

Modules list

LPUART1

LPUART2

LPUART3

LPUART4

LPUART5

LPUART6

LPUART7

LPUART8

LPUART9

LPUART10

LPUART11

LPUART12

UART Interface

Connectivity

Peripherals

Each of the UART modules support the following serial

data transmit/receive protocols and configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable

parity (even, odd or none)

• Programmable baud rates up to 20 Mbps.

MECC64

Error Correcting Code

Memories and

Memory Controllers

MECC64 module supports Single Error Correction and

Double Error Detection (SECDED) ECC function to

provide reliability for 4 banks On-Chip RAM (OCRAM)

access. When ECC function is disabled, ECC OCRAM

can be also used to store data.

MIPI-CSI

MIPI CSI Interface

Multimedia

Peripherals

Key features of MIPI CSI controller are listed as

following:

• Implements all three MIPI CSI-2 layers

• Supports CSI-2 Unidirectional Master operation

• Virtual Channel support

• Flexible pixel-based user interface

MIPI-DSI

MIPI DSI Interface

Multimedia

Peripherals

Key features of MIPI DSI controller are listed as

following:

• Implements all three DSI layers

• Supports Command and Video Modes

• Virtual Channel support

• Flexible packet based user interface

MQS

Medium Quality Sound

Multimedia

Peripherals

MQS is used to generate 2-channel medium quality

PWM-like audio via two standard digital GPIO pins.

Messaging Unit

System Control

The Messaging Unit module enables two processors

within the SoC to communicate and coordinate by

passing messages (e.g. data, status, and control)

through the MU interface.

The MU also provides the ability for one processor to

signal the other processor using interrupts.

Table 3. i.MX RT1170 modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

PIMXRT516SCVJ2A Datasheet(PDF) 16 Page - NXP Semiconductors

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