PIMXRT516SCVJ2A datasheet(21/128 Pages) NXP

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Modules list

i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021

NXP Semiconductors

RTC_XTALI/RTC_XTALO To hit the exact oscillation frequency, the board capacitors must be reduced to account for the

board and chip parasitics. The integrated oscillation amplifier is self-biasing, but relatively weak.

Care must be taken to limit the parasitic leakage from RTC_XTALI and RTC_XTALO to either the

power or the ground (> 100 M). This de-biases the amplifier and reduces the start-up margin.

If you want to feed an external low-frequency clock into RTC_XTALI, the RTC_XTALO pin must

remain unconnected or driven by a complementary signal. The logic level of this forcing clock must

not exceed the VDD_SNVS_DIG level and the frequency shall be < 100 kHz under the typical

conditions.

It is recommended to tie RTC_XTALI to GND if external crystal is not used. When a high-accuracy

real-time clock is not required, the system may use the on-chip 32 kHz oscillator. The tolerance is

10%. The ring oscillator starts faster than the external crystal and is used until the external crystal

reaches a stable oscillation. The ring oscillator also starts automatically if no clock is detected at

RTC_XTALI.

XTALI/XTALO

The SDK software requires 24 MHz on XTALI/XTALO. The crystal can be eliminated if an external

24 MHz oscillator is available in the system. In this case, refer to section of Bypass Configuration

(24 MHz) from the reference manual. There are three configurations that can be utilized, but

configuration 2 is recommended.

The logic level of this forcing clock must not exceed the VDD_LPSR_ANA level.

If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter

requirements. See Section 4.2.6, On-chip oscillators and relevant interface specifications chapters

for details.

JTAG_nnnn

External resistors can be used with all JTAG signals except for JTAG_TDO, but they are not

required. See Table 5 for a summary of the JTAG interface.

JTAG_TDO is configured with an on-chip keeper circuit, such that the floating condition is actively

eliminated if an external pull resistor is not present. An external pull resistor on JTAG_TDO is

detrimental. See Table 5 for a summary of the JTAG interface.

When JTAG_MOD is low, the JTAG interface is configured for a common software debug, adding

all the system TAPs to the chain.

When JTAG_MOD is high, the JTAG interface is configured to a mode compliant with the IEEE

1149.1 standard.

These signals are No Connect (NC) and should not be connected by the user.

POR_B

See the System Boot chapter in the reference manual for the correct boot configuration. Note that

an incorrect setting may result from an improper boot sequence.

POR_B signal has internal 100 k

 pull up to SNVS domain, should pull up to VDD_SNVS_ANA if

need to add external pull up resistor, otherwise it will cause additional leakage during SNVS mode.

It is recommended to add the external reset IC to the circuit to guarantee POR_B is properly

processed during power up/down, please refer to the EVK design for details.

Note:

• As the Low DCDC_IN detection threshold is 2.6 V, the reset IC’s reset threshold must be higher

than 2.6 V, then the whole chip is reset before the internal DCDC module reset to guarantee the

chip safety during power down.

• For power on reset, on any conditions ones need to make sure the voltage on DCDC_PSWITCH

pin is below 0.5 V before power up.

ONOFF

A brief connection to GND in the OFF mode causes the internal power management state machine

to change the state to ON. In the ON mode, a brief connection to GND generates an interrupt

(intended to be a software-controllable power-down). Approximately five seconds (or more) to GND

causes a forced OFF. Both boot mode inputs can be disconnected.

TEST_MODE

This input is reserved for NXP manufacturing use. The user must tie this pin directly to GND.

Table 4. Special signal considerations (continued)

Signal Name

Remarks

PIMXRT516SCVJ2A Datasheet(PDF) 21 Page - NXP Semiconductors

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